Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2000-01-31
2001-04-24
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S088000, C326S083000, C326S087000, C326S119000, C326S121000
Reexamination Certificate
active
06222390
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to digital circuits and, more particularly to a method and circuit for recycling charge in digital circuits.
2. Background Information
For integrated circuits and, in particular, integrated circuits including digital electronic circuits, the frequency of operation and integrated circuit transistor count for such circuits continues to increase as semiconductor technology continues to advance. As a result, the power consumption of an integrated circuit also continues to increase. However, reducing the power consumption of an integrated circuit is desirable, especially for mobile or portable applications, such as laptop computers, cellular telephones and the like.
Typically, power consumption has been reduced by reducing the power supply voltage level. Reducing the power supply voltage level has been beneficial because power consumption is proportional to the square of the voltage level. However, a lower limit exists on the ability to reduce the supply voltage level due at least partially to transistor threshold voltage levels. Therefore, another technique to reduce power consumption would be desirable.
A charge recycling differential logic circuit that has been developed is one example to reduce power consumption. See, for example, “Charge Recycling Differential Logic (CRDL) for Low Power Application” by Bai-Sun Kong, Joo-Sun Choi, Seog-Jun Lee, and Kwyro Lee, appearing in
IEEE Journal of Solid
-
State Circuits,
Vol. 31, No. 9, September 1996, herein incorporated by reference. In this article, a technique is described in which digital signals are converted into differential signals and a precharge clock phase is employed to redistribute charge in the circuit. During an evaluation clock phase, a sense amplifier is employed and then generates the digital output signals. This approach reduces power consumption compared to domino logic circuit approaches. However, this approach also consumes more power than static complementary metal-oxide-semiconductor (CMOS) circuits. In particular, the interconnect loading is doubled in comparison with a static CMOS circuit because the digital signals are converted to differential pair signals. Likewise, additional gates are employed for overhead and these additional gates consume additional power.
A need, therefore, exists for a circuit or technique for reducing power consumption relative to static CMOS circuits.
SUMMARY OF THE INVENTION
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes.
Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors.
Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.
Briefly, in accordance with still another embodiment of the invention, a method of recycling charge includes: applying complementary voltage signals to first and second transistors coupled in an integrated circuit so as to substantially evenly distribute electrical charge between output nodes.
REFERENCES:
patent: 4129793 (1978-12-01), Bula et al.
patent: 4639622 (1987-01-01), Goodwin et al.
patent: 5194764 (1993-03-01), Yano et al.
patent: 5367205 (1994-11-01), Powell
patent: 5369320 (1994-11-01), Satani et al.
patent: 5371424 (1994-12-01), Quigley et al.
patent: 5455802 (1995-10-01), McClure
patent: 5471415 (1995-11-01), McClure
patent: 5489859 (1996-02-01), Kawaguchi et al.
patent: 5514993 (1996-05-01), Adachi
patent: 5517129 (1996-05-01), Matsui
patent: 5602795 (1997-02-01), Sandhu
patent: 5617043 (1997-04-01), Han et al.
patent: 5694061 (1997-12-01), Morosawa et al.
patent: 5736888 (1998-04-01), Sharpe-Geisler
patent: 5929656 (1999-07-01), Pagones
Kong B-S, et al., “Charge Recycling Differential Logic (CDRL) for Low Power Application,” IJSSC, vol. 31, No. 9, pp. 1267-1276, Sep. 1996.
Intel Corporation
Skaist Howard A.
Tan Vibol
Tokar Michael
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