Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-05-10
2001-04-17
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S587000, C257S385000
Reexamination Certificate
active
06218272
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a conductive pad for a bit line/storage electrode of a DRAM (dynamic random access memory) device.
BACKGROUND OF THE INVENTION
Over the years, the development fabrication of fine and high integrated semiconductor devices has been actively pursued. Even more recently, a VLSI (very large scale integration) semiconductor device, such as giga-bit DRAM (dynamic random access memory) designed according to a 256 mega-bit design rule or under a 0.25 &mgr;m size rule, is being developed and fabricated. As high integration of semiconductor devices is performed, it becomes more increasingly desired to enhance mask aligned margin of a lithography process which is essential to formation of a semiconductor components structure.
When a semiconductor device is normally fabricated, patterns which are formed of various materials such as a metal layer, a semiconductor layer, and an insulating layer gradually become thin on a semiconductor substrate, thereby forming a fine semiconductor components structure. When these patterns for semiconductor components become thin, it is required that a mask be aligned to a pattern in a lower layer formed during a former process and then, an upper layer pattern be formed during a lithography process. However, misalignment between an upper layer and an lower layer pattern may occur during the lithography process. Accordingly, it is required to leave room preventing misalignment in a pattern spacing, so as to set up a margin therein. But the margin may be in the way of high integration of the pattern.
The technical methods obtaining a margin-less structure are examined from many sources. In these technical methods, it is important to obtain a margin-less structure especially while forming a contact hole. Since the contact hole is formed on a semiconductor substrate and many layers of a semiconductor layer and a metal layer, the formation of a margin-less contact hole is the most effective to achieve high density/high integration of a semiconductor device. The effective methods among techniques for fabricating a margin-less contact hole include a method for forming a self-aligned contact hole. In addition, other various and reliable methods have also been investigated. These methods for forming a self-aligned contact hole include a reverse active type self-aligned contact (referring to below as RAT-SAC) process and a contact type self-aligned contact (referring to below as CT-SAC) process.
A typical technology of the former process is published in an article entitled “240 nm Pitch 4GDRAM Array MOSFET Technologies with X-ray Lithography” in IEDM 96 and “A Fully Printable, Self-aligned and Planarized Stacked Capacitor DRAM Cell Technology for 1 Gbit DRAM and Beyond” in Symposium on VLSI Technology Digest of Technical Papers, 1997. On the other hand, a typical technology of the latter process is published in an article entitled “A Process Technology for 1 Giga-Bit DRAM” in IEDM 95 and “A New Planar Stacked Technology (PST) for scaled and Embedded DRAMs” in IEDM 96.
FIG. 1A
illustrates a cell array layout of a DRAM device having a contact hole (for example, a storage electrode and contact holes for a bit line pad) which is formed by using the RAT-SAC process. A gate electrode (or word line)
10
, a self-aligned buried contact
12
(hereinafter referred to as BC) connecting a storage electrode to a semiconductor substrate, a self-aligned direct contact
14
(hereinafter referred to as DC) connecting a bit line to a semiconductor substrate are illustrated in FIG.
1
A. An active region where a device is formed is formed of a T-shaped structure, as shown by the dotted line of FIG.
1
A.
FIG. 1B
illustrates a cross-sectional view taken along a line
1
-
1
′ of FIG.
1
A. If a photo etching process for forming a contact hole is performed by the RAT-SAC process, as shown in
FIG. 1B
, an opening forming a bit line and pads for a storage electrode is formed according to a shape of an active region wherein two switching transistors comprising a memory cell are formed. Thus, a relatively wider opening region may be obtained using this process in comparison with the latter process, hereinafter described. In the RAT-SAC process, an electrical short of gate to pad may be prevented. The short results from the etching of a gate shoulder portion (a shoulder portion of an upper layer of a gate electrode serving as an etch-stop layer). However, because etching a nitride layer, which serves as a capping layer, the height (referring to below as step) between a gate electrode
10
and a nitride layer
17
maybe reduced to a part marked by a dotted line. At this time, the capping layer may protect a gate electrode while performing an etching process when an opening is formed.
As a result, it is difficult to secure an original purpose (to secure misalignment margin), as illustrated in FIG.
1
B. That is, in the SAC process using an etch selectivity, it is ideal that a conductive layer (for example, a doped polysilicon) for a pad
18
should be filled to a dotted line
20
shown in FIG.
1
B. However, in the substantial RAT-SAC process, a conductive layer is filled to a dotted line
22
shown in
FIG. 1B
(a pad of a surface should be formed under an insulating layer
17
surrounding a gate electrode
10
so as to prevent short of pad to pad). A size of a finally formed pad
18
may be formed less than a desirable size
20
. Limited to a spacing between one gate and another gate, a size of a pad is reduced in proportion to integration of a semiconductor memory device, in FIG.
1
A. Consequently, it is difficult to obtain the aforesaid margin-less structure (to achieve the original purpose of a self-aligned contact). Further, as mentioned above, an upper surface of the pad is formed between gate electrodes, so that the size thereof is reduced and the process margin (that is, misalignment margin) is rapidly reduced when a contact hole for connecting a storage electrode or a bit line to a semiconductor substrate is formed. As a result, when a device is substantially operated, soft refresh fail occurs.
FIG. 2A
illustrates a cell array of a DRAM device having a contact hole (for example, a contact hole for a storage electrode and a bit line) formed by using the CT-SAC process. The same reference numerals in
FIG. 2B
denote the same elements in FIG.
1
A. In case a contact hole is formed by using the CT-SAC process, as shown in
FIG. 2A
, the BC
12
is formed to be relatively less than the DC
14
.
FIG. 2B
illustrates a cross-sectional view taken along a line
2
-
2
′ of FIG.
2
A.
If a contact hole is formed using the CT-SAC process, a process resultant is obtained, as shown in FIG.
2
B. According to the CT-SAC process, contact holes for the BC/DC are formed of a circle-shape or an ellipse-shape. After formation of a photoresist pattern, an etching process is performed to form the contact hole. An opening region corresponding to an active region is secured, in the RAT-SAC process. On the other hand, an opening region is small with a circle-shape or an ellipse-type, in the CT-SAC, as shown in FIG.
2
A. Since an etch selectivity of the RAT-SAC process is relatively lower than that of CT-SAC process (at this time, a not-open may occur), etching time should be increased to overcome the lower etch selectivity. As a result, a shoulder portion of a gate electrode
10
is overetched to create an exposure thereof (to create electrical short of pad to gate electrode).
In addition, as described in
FIG. 2A
, since the BC
12
is formed less than the DC
14
, a gate shoulder portion related with the DC
14
should be relatively more etched than a gate shoulder portion related with the BC
12
so as to form a contact hole having an equal depth.
Consequently, an etch selectivity of a nitride layer with respect to an interlayer insulating film is not secured to expose a gate electrode, as mentioned above.
A technique solving fundament
Lee Kyu-pil
Yeom Kye-Hee
Cantor & Colburn LLP
Chaudhuri Olik
Peralta Ginette
Samsung Electronic Co. Ltd.
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