Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-01-22
2001-07-10
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S127000, C711S163000, C711S165000, C711S167000, C711S170000, C711S173000
Reexamination Certificate
active
06260122
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention generally relates to a memory device into which data from the preceding stage is written and from which data is read depending on the processing status of the subsequent stage, and more particularly to a memory device of which a required memory capacity is split into a plurality of split memories for use in processing.
2. Description of the Related Art
Conventionally, encoding and compressing processing have been performed in recording and transmitting of audio data or image data, and decompressing and decoding processing have been performed in reproducing and receiving.
For example, in recording an audio signal in an MD (minidisc), the audio signal is first converted into digital delta (A/D conversion), and in turn the digital data is split into three bands (frequency bands) comprising a low, an intermediate, and a high band by a digital filter called a QMF (Quadrature Mirror Filter), and subjected to MDCT (Modified Discrete Cosine Transform) processing, quantization processing, and the like, and the resultant data is written into the MD. Accordingly, reproduction of such data involves reverse processing such as dequantization, IMDCT (Inverse MDCT) processing, inverse filtering processing by IQMF (Inverse QMF), D/A conversion, and the like.
When performing such processing, a memory is required to store the data being processed in the process of the processing. For example, when the MDCT processing is performed, data fed from the QMF at the preceding stage is processed, wherein L channel data and R channel data are alternately fed from the QFM in time series. On the other hand, in the MDCT processing, the L channel data and the R channel data are separately processed.
Accordingly, data required for the processing is kept stored, and at the stage when the data to be processed is all available, the processing is started. Thus, the processing requires a memory for storing the data to be processed and for storing the data inputted thereto while the processing is being performed. Further, calculations associated with the MDCT involve recursive operations, thus also requiring a memory for storing data being processed.
For the MDCT processing, a large quantity of data is to be stored as mentioned above, causing a problem that a large capacity memory (generally SRAM) is required.
Besides, in the MDCT, data is split into SGs (Sound Group) each having a period of 11.6 msec for processing. At a boundary of two SGs, data is used overlapped to a degree by both SGs. Therefore, the overlapped data is used in the MDCT relating to the two SGs. For this reason, the data used twice must be prevented from being overwritten by the following data.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a memory device which is capable of efficient processing.
The present invention is directed to a memory device in which memory capacity required for processing a predetermined quantity of data is split into a plurality of split memories for use in the processing, wherein the plurality of the above mentioned split memories is composed of a first memory group storing data to be processed during a predetermined processing duration and a second memory group for being written into and storing data being inputted in the course of the processing duration, and the first memory group and the second memory group are alternately switched at a time point where the predetermined processing duration has passed excepting at least one of the split memories. As roles of memories are switched in this way leaving a part thereof intact, input data can be received while data to be used for processing can efficiently be held. Accordingly, processing with reduced memory capacity is made possible.
In a preferred aspect of the present invention, the above mentioned first group is allocated a larger number of the split memories than the above mentioned second group.
In another preferred aspect, the at least one split memory of the above mentioned first memory group continuously hold data even after the predetermined processing duration has passed.
REFERENCES:
patent: 5295252 (1994-03-01), Torri et al.
patent: 5537577 (1996-07-01), Sugimura et al.
patent: 5689680 (1997-11-01), Whittaker et al.
patent: 5761695 (1998-06-01), Maeda et al.
patent: 5761714 (1998-06-01), Liu et al.
patent: 5761732 (1998-06-01), Shaberman et al.
patent: 5805855 (1998-09-01), Liu
patent: 5828671 (1998-10-01), Vela et al.
patent: 5924117 (1999-07-01), Luick
patent: 5960462 (1999-09-01), Solomon et al.
patent: 6049855 (2000-04-01), Jeddeloh
Matsui Masaru
Nagao Fumiaki
Cantor & Colburn LLP
Kim Matthew
Sanyo Electric Co,. Ltd.
Tzeng Fred F.
LandOfFree
Memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2461044