Si-Ge CMOS semiconductor device

Details Si-Ge CMOS semiconductor device Si-Ge CMOS semiconductor device

1996-12-13

2001-08-07

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06271551

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device comprising a semiconductor body of silicon with a p-type surface region adjoining a surface and provided with an n-type channel field effect transistor with insulated gate and with n-type source and drain zones provided in the surface region and mutually separated by an interposed channel region also adjoining the surface, while the surface region is provided with a buried p-type doped zone which extends below the channel region at a small distance from the surface and which has a higher doping concentration than the channel region. Such a device is known from U.S. Pat. No. 5,166,765.
The mobility of the charge carriers in the channel, often indicated with the symbol &mgr; and expressed in cm
2
/V.s, is an important parameter in MOS transistors with channel dimensions in the deep sub-micron region (for example, 0.1 micron), inter alia in view of the capacity of the transistor to conduct current. The mobility is strongly dependent on the value of the electric field in the channel, at least on the component of the field transverse to the surface. In general, the mobility decreases with an increasing field strength. The doping concentration in the channel should accordingly be very low in order to obtain a high mobility, for example of the order of 10
15
atoms per cm
3
(intrinsic silicon). Such a low doping level, however, is not possible because punch-through to the source occurs at very low drain voltages already with this doping. In addition, low channel doping levels in combination with very small dimensions (for example, a channel surface area of 0.1 &mgr;m×0.1&mgr;m) may lead to major fluctuations in the threshold voltage, which may be particularly unfavorable at lower supply voltages owing to fluctuations in the doping level. These problems are solved in principle in a transistor as described in the cited U.S. Pat. No. 5,166,765. In this known transistor, the channel region comprises an intrinsic surface region which adjoins the surface, has a thickness of a few tens of nanometers, and is situated above and adjoining a thin p-type layer having a high concentration of boron atoms, for example of the order of 10
18
per cm
3
. A transistor constructed in this way has a high mobility of charge carriers, a high punch-through voltage, and a good threshold voltage. The extremely small dimensions, however, render it difficult to manufacture such a transistor in a reliable and reproducible manner. Moreover, a separate implantation of As ions is required in the channel region of the transistor so as to compensate for the B atoms present and make the silicon in the channel region intrinsic. Such an As implantation in the channel, however, is disadvantageous for the mobility of the charge carriers and for the process control, for example as regards the threshold voltage V
T
.
SUMMARY OF THE INVENTION
The invention has for its object to provide a device of the kind described in the opening paragraph which can be manufactured in a reliable and reproducible manner. The invention also has for its object to provide such a device in which a separate As implantation in the - intrinsic - channel region is unnecessary, so that the mobility in the channel is not adversely affected by impurities.
According to the invention, a semiconductor device of the kind described in the opening paragraph is characterized in that the surface region is in addition provided with a buried Si
1−x
Ge
x
layer (called SiGe layer hereinafter), x representing the molar fraction of Ge, extending below the channel region and forming a diffusion barrier between the comparatively weakly doped channel region adjoining the surface and the comparatively strongly doped buried p-type zone.
The invention is based inter alia on the recognition that the diffusion of boron atoms to the surface may be fairly strong owing to the small depth of the buried p-type zone, in particular because of the growing of the gate oxide during which empty places arise in the crystal lattice which promote the diffusion of boron atoms. The invention is further based on the recognition that this diffusion may be decelerated by a SiGe layer whose thickness is so small that the lattice distances, at least in a direction parallel to the surface, are equal or at least substantially equal to the lattice constants in the silicon crystal. This renders it possible to form the channel region through epitaxy of intrinsic silicon on the SiGe layer. The gate oxide may be formed in a subsequent step, during which the diffusion of boron atoms is decelerated by the SiGe layer.
It is noted that, wherever reference is made to an SiGe layer below, this should be understood to include all layers in which Si is replaced by Ge in a number of lattice points of the crystal. Besides Ge, the layer may comprise other substances, for example C, as long as the layer is electrically conducting, diffusion-inhibiting, and monocrystalline, so that an intrinsic silicon layer can be epitaxially deposited on the layer. The SiGe layer may be formed through implantation of Ge into the silicon crystal. This, however, leads to major damage in the crystal, in particular when the Ge content becomes greater, for example when x is approximately 0.3. A major preferred embodiment of a semiconductor device according to the invention, which has the advantage that the composition of the SiGe layer may be chosen within wide limits, is characterized in that the SiGe layer and the channel region adjoining the surface are formed by epitaxial layers.
Conventional separation techniques such as thick field oxide may be used for the lateral boundaries of the active regions in the semiconductor body. Since a thermal treatment of long duration is less desirable after the application of the SiGe layer and the intrinsic layer, the field oxide is preferably provided first, after which the SiGe layer and the intrinsic layer are deposited in the active regions, for example by selective epitaxy. An embodiment in which the provision of the lateral boundaries does not require a high-temperature step of long duration and in which the lateral boundaries can be provided after the SiGe layer has been deposited, is characterized in that the transistor is laterally bounded in the semiconductor body by grooves which may or may not be filled up with a filler material and which extend from the surface into the semiconductor body to a depth which is greater than the depth of the source and drain zones.
The invention may be used to advantage in integrated circuits with exclusively n-channel field effect transistors. An important class of integrated circuits comprises complementary field effect transistors (CMOS) in which p-channel transistors are present as well as n-channel transistors. A semiconductor device incorporating a further aspect of the invention is characterized in that at the area of an n-type surface region adjoining the surface the semiconductor body is provided with a p-channel field effect transistor with insulated gate and with p-type source and drain zones which are provided in the n-type surface region and are mutually separated by an interposed channel region, the n-type surface region being provided with a buried n-type zone below the channel region, which zone is doped with As or Sb with a doping concentration higher than that of the channel region adjoining the surface and that of a buried Si
1−x
Ge
x
layer. This aspect of the invention is based inter alia on the recognition that it is desirable also for the p-channel transistor that a strongly doped n-type layer should be provided at a depth of a few tens of nanometers from the surface for reasons analogous to those for the n-channel transistor. SiGe, however, does not form a diffusion barrier for n-type impurities. Accordingly, the channel region would be strongly doped by the buried layer when P is used, which has a diffusion constant comparable to that of B. The use of the n-type dopant As, or possibly Sb, renders it possible to choose the process co

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