Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-07-02
2001-05-29
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S239000, C438S241000, C438S253000, C438S258000, C438S287000
Reexamination Certificate
active
06239010
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing a capacitor and an interconnect. More particularly, the present invention relates to a method for manufacturing a capacitor and an interconnect of a mixed-mode circuit.
2. Description of Related Art
A mixed-mode circuit device typically includes a circuit comprising both digital and analog devices in a logic area of a semiconductor chip. The digital devices include inverters, adders, and the analog devices include amplifiers and analog-to-digital converters. Currently, the mixed-mode circuit device comprises a capacitor structure. In the common mixed-mode logic manufacturing process, double polysilicon layers are used as capacitor electrodes. The capacitor with double polysilicon layers as electrodes are called a double polysilicon capacitor (DPC).
FIG. 1
is schematic, cross-sectional view of a conventional double polysilicon capacitor. Conventionally, the method for manufacturing a double polysilicon capacitor comprises the steps of forming a thin oxide layer (not shown) and a polysilicon layer (not shown) on a substrate
100
and an isolation region
116
, and then patterning the thin oxide layer and the polysilicon layer to form a polysilicon gate electrode
106
and gate oxide layer
104
of a field effect transistor
110
and to form a bottom electrode
108
of a double polysilicon capacitor
102
. The field effect transistor
110
is located on the substrate
100
and the bottom electrode
108
is located on the field oxide layer
116
. After that, a dielectric layer (not shown) and a polysilicon layer (not shown) are formed on the substrate
100
and then the dielectric layer and the polysilicon layer are patterned to form a capacitor dielectric layer
112
and an upper electrode
114
of the double polysilicon capacitor
102
.
The thickness of the polysilicon layer used to form the bottom electrode
108
is different from that of the polysilicon layer used to form the upper electrode
114
, so that the polysilicon layer on the sidewall of the bottom electrode
108
is difficult to remove in the patterning process. The stringer effect easily occurs.
Additionally, in order to increase the conductivity of the bottom electrode
108
and the upper electrode
114
, dopants are implanted into the bottom electrode
108
and the upper electrode
114
. However, the resistance of the bottom electrode
108
and the upper electrode
114
is still high. Moreover, when the mixed-mode device is operated, the dopants in the capacitor are affected by the supplied voltage to form a depletion region at the interface between the capacitor dielectric layer
112
and the bottom electrode
108
and at the interface between the capacitor dielectric layer
112
and the upper electrode
114
. The depletion region is considered an extension of the thickness of the capacitor dielectric layer
112
. Nevertheless, the charge storage ability of the capacitor
102
is related to the thickness of the capacitor dielectric layer
112
. The charge storage ability of the capacitor worsens as the thickness of the capacitor dielectric layer
112
increases. Therefore, the capacitance of the capacitor
102
is decreased and the operation efficiency of the devices is decreased. Furthermore, the thickness of the depletion region varies with the supplied voltage, that leads to an increase voltage coefficient (1/C, dC/dV) for the capacitor. Hence, the capacitance of the capacitor
102
varies with the supplied voltage and the devices are unstable.
In the analog circuit, the capacitance is used as a converting basis for the time delay (□, □=RC), so that the accuracy capacitance requirement of the analog devices is very critical. Incidentally, the operation efficiency is greatly affected by the increase of the voltage coefficient.
Additionally, the capacitor
102
is a two-dimensional capacitor. The surface of the capacitor
102
is increased to increase the capacitance. However, the increase of the capacitor surface leads to decreased device integration.
SUMMARY OF THE INVENTION
The invention provides a method for manufacturing a capacitor for a mixed-mode circuit. A substrate is provided. An isolation region is formed on the substrate to define an active region in the substrate. An oxide layer, a first polysilicon layer and a first silicide layer are formed over the substrate. The oxide layer, the first polysilicon layer and the first silicon layer are patterned to form a gate structure on the active region and to form a first polysilicon electrode and a first silicide electrode on the isolation region. A dielectric layer is formed over the substrate. An opening is formed to expose a portion of the first silicide electrode. A second silicide layer is formed on a sidewall and a bottom of the opening and on the dielectric layer. A planarization process is performed to remove a portion of the second silicide layer above the dielectric layer, wherein the remaining second silicide layer in the opening, the silicide electrode and the polysilicon electrode together form a bottom electrode of the capacitor. A capacitor dielectric layer is formed over the substrate. A first metal layer is formed over the substrate. The first metal layer is patterned to form an upper electrode of the capacitor.
The invention provides a method of manufacturing a capacitor for a mixed-mode circuit. A substrate is provided. A first metal layer is formed on the substrate. The first metal layer is patterned to form a first wire and a first bottom electrode. A dielectric layer is formed over the substrate. An opening is formed to expose a portion of the first bottom electrode. A second metal layer is formed on a sidewall and a bottom of the opening and on the dielectric layer. A planarization process is performed to remove a portion of the second metal layer above the dielectric layer, wherein the remaining second metal layer in the opening and the first bottom electrode together form a second bottom electrode of the capacitor. A capacitor dielectric layer is formed over the substrate. A third metal layer is formed over the substrate. The third metal layer is patterned to form a first upper electrode of the capacitor.
As embodied and broadly described herein, the invention provides a method for manufacturing a capacitor of a mixed-mode circuit. Because both of the upper electrode and the bottom electrode are made of metal, the resistance of the capacitor is low and the operation efficiency can be greatly improved. Moreover, the stability problem caused by the doped electrodes can be overcome. Furthermore, since the capacitor formed in the opening is a three-dimensional capacitor, the surface of the capacitor is increased and the integration of the devices is not decreased with the increasing of the surface of the capacitor. Incidentally, the stringer effect due to the difference between the polysilicon layers will not occur in the invention, so that the reliability of the devices is increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5079670 (1992-01-01), Tigelaar et al.
patent: 6066528 (2000-05-01), Fazan et al.
patent: 6096619 (2000-08-01), Yamamoto et al.
Kennedy Jennifer M.
Tsai Jey
United Microelectronics Corp.
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