Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-04-26
2001-09-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S241000, C438S462000, C438S599000, C438S622000, C438S926000, C257S296000, C257S306000, C257S572000, C257S578000, C257S773000
Reexamination Certificate
active
06287948
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for making pattern data.
2. Description of Related Art
An interlayer dielectric layer provided in a semiconductor device has roles in insulating an upper wiring layer from a lower wiring layer, for example. If the interlayer dielectric layer does not have a flat surface, problems arise in that wiring layers formed on the interlayer dielectric layer may be cut.
Interlayer dielectric layers having an excellent planarization characteristic includes, for example, a silicon oxide film that is formed by reacting a silicon compound such as silane with hydrogen peroxide through a CVD method. For example, this technology is described in Japanese Laid-open Patent Application HEI 9-102492.
Although such a silicon oxide film is used as an interlayer dielectric layer, a global height difference is created along a border between a region in which large patterns of wiring layers are formed and a region in which small patterns of wiring layers are formed. More specifically, a main surface of a semiconductor substrate includes a region where relatively large patterns of wiring layers are formed and a region where smaller patterns of wiring layers are formed. The silicon oxide film has a high level of flowability. Accordingly, the silicon oxide film formed over the region where the small patterned wiring layers are formed typically has a thickness smaller than the thickness of the silicon oxide film formed over the region where the large patterned wiring layers are formed. Due to the thickness difference, a global height difference is created.
As the number of wiring layers increases, the number of interlayer dielectric layers increases. A difference in thickness occurs in each interlayer dielectric layer, and the thickness differences are added up. Accordingly, as the number of interlayer dielectric layers increases, the global height difference becomes greater.
Problems caused by greater global height differences are discussed below. When a through hole is formed in an interlayer dielectric layer, a resist is used. A focus margin in exposing the resist becomes smaller when the global height difference becomes larger. As a result, the resolution at the resist lowers. As a consequence, a designed shape of a through hole may not be formed or a through hole may not be formed at all.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having a structure that is capable of reducing the global height difference and a method of making pattern data for the semiconductor device.
In accordance with one embodiment of the present invention, a semiconductor device has a global height difference in a border region between a first region and a second region. The semiconductor device comprises an interlayer dielectric layer, a first wiring layer, a second wiring layer, a first dummy pattern and a second dummy pattern. The first wiring layer is located in the first region and is formed from a small pattern. The second wiring layer is located in the second region and is formed from a relatively large pattern. The interlayer dielectric layer covers the first region and the second region. The interlayer dielectric layer includes a planarization silicon oxide film. The interlayer dielectric layer, located over the first wiring layer, has a thickness smaller than the thickness of the interlayer dielectric layer located over the second wiring layer such that the global height difference occurs in the border region between the regions. The first dummy pattern is formed in the first region, and the second dummy pattern is formed in the border region.
As a result, the first region and the border region can be formed into a condition that is equal to the condition in which the large pattern of wiring layer is located. For example, the pattern density in the first region where the smaller patterns are formed can be made generally equal to the pattern density in the second region where the larger patterns are formed because of the dummy pattern formed in the first region. Accordingly, the interlayer dielectric layer, covering the first region and the second region, can have generally the same thickness, and thus a smaller global height difference may be created in a semiconductor device. As a consequence, for example, a sufficient focus margin can be secured when a resist on an interlayer dielectric layer is exposed (for example, by a reduction projection exposure, an equal magnification (1:1) projection exposure or a scanning-type reduction projection exposure), and thus the resolution with respect to the resist is improved. Consequently, a through hole having a desired shape can be formed in an interlayer dielectric layer.
In accordance with one embodiment of the present invention, a large pattern has a width that is greater than the width of a small pattern. In a preferred embodiment, a large pattern may have a width ranging from several ten &mgr;m to several hundred &mgr;m, for example. A small pattern may have a width ranging from 0.1 &mgr;m to several &mgr;m.
In accordance with the present invention, a global height difference refers to a step difference that is created because the thickness of the interlayer dielectric layer located above the small pattern wiring layer is thinner than that of the interlayer dielectric layer located above the large pattern wiring layer.
In a semiconductor device in accordance with one embodiment of the present invention, for example, a minimum distance between the first wiring layer and the first dummy pattern, a minimum distance between the first wiring layer and the second dummy pattern and a minimum distance between the second wiring layer and the second dummy pattern, are respectively a minimum processible dimension for manufacturing the semiconductor device. On the other hand, a maximum distance between the first wiring layer and the first dummy pattern, a maximum distance between the first wiring layer and the second dummy pattern and a maximum distance between the second wiring layer and the second dummy pattern, are respectively a wiring layer width on a design rule for the semiconductor device.
The minimum distance is set to be a minimum processible dimension in manufacturing the semiconductor device because of the following reasons. The minimum processible dimension refers to a minimum dimension that can be obtained by the available semiconductor device manufacturing process and the semiconductor device manufacturing apparatus. A minimum distance between the first wiring layer and the first dummy pattern, a minimum distance between the first wiring layer and the second dummy pattern, and a minimum distance between the second wiring layer and the second dummy pattern may preferably be as small as possible, because the placement conditions of the regions where the first wiring layer, the first dummy pattern and the second dummy pattern are located become more similar to the placement condition of an area where the large pattern wiring layer is disposed. However, since these distances cannot be made shorter than a minimum processible dimension in manufacturing a semiconductor device, they are set to be a minimum processible dimension in manufacturing a semiconductor device.
The maximum distance is set to be a wiring layer width on a design rule for the semiconductor device because of the following reasons. As discussed above, the smaller the distance between a wiring layer and a dummy pattern becomes, the more the planarization effect improves. On the other hand, the greater the distance between a wiring layer and a dummy pattern becomes, the more the planarization effect deteriorates. When the maximum distance is set to be a wiring layer width on a design rule for the semiconductor device or less, patterns can be formed with sufficient focus margins without taking extraordinary measures, such as changing the design rule and the like.
In accordance with one embodiment of the present invention, the planariza
Anya Igwe U.
Hogan & Hartson L.L.P.
Seiko Epson Corporation
Smith Matthew
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