Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-30
2001-05-08
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S905000, C257S907000
Reexamination Certificate
active
06229170
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory cell having a pair of switching transistors, each of which is connected to a bit line through a bit line contact.
2. Description of the Related Art
A memory unit of a dynamic Random Access Memory (hereinafter, referred to as a DRAM) is composed of one MOS transistor (hereinafter, referred to as switching transistor)
401
and one capacitor (hereinafter, referred to as capacitor )
402
, as shown in
FIG. 1. A
gate of switching transistor
401
is connected to word line
404
, and source and drain thereof are connected to bit line
403
. Stored data is stored in capacitor
402
as a charge, and data is stored or discharged in/from capacitor
402
depending on switching ON/OFF of switching transistor
401
.
The charge stored/discharged in/from capacitor
402
is interchanged between capacitor
402
and an external circuit through bit line
403
which is connected to the opposite side of switching transistor
401
to capacitor
402
. A signal for determining ON/OFF of switching transistor
401
is supplied to switching transistor
401
through word line
404
which is connected to the gate of switching transistor
401
or formed integrally with the gate thereof.
The DRAM is composed of one transistor and one capacitor as constitution components, and it has an excellent advantage that it can achieve a reduction in an area of the memory cell because of its small number of constitution components.
As downsizing of the memory cell and increasing of memory cell density thereof are promoted, the DRAM cell has been developed in its structure from a planar capacitor cell in which a capacitor is formed on a diffusion layer two-dimensionally to a stacked capacitor cell in which the capacitor is formed three-dimensionally on the word line. However, with further reduction of the cell area, as shown in FIG.
2
A and
FIG. 2B
, shield bit line type stacked cell in which a capacitor is formed on bit line
485
is proposed in IEDM (International Electron Device Meeting) Technical Digest, pp. 592-595, 1988 and pp. 596-599, 1988.
In these structures, the capacitor is disposed in the uppermost layer thereof, and the bit line is disposed between the capacitor and the word line. Therefore, a contact for connection with other elements is never formed at the position of the capacitor element, an area occupied by the capacitor can be secured to the utmost limit, so that the DRAM takes a structure that is advantageous for securing a capacitance.
FIG.
2
A and
FIG. 2B
illustrate, a plan view and a section view, respectively, of the conventional shield bit line type stacked cell, proposed in IEDM, pp 592-595, 1988.
FIG. 3
is a view showing an active region pattern alone in the plan view of FIG.
2
A. As is apparent from
FIG. 2B
, in this conventional memory cell, an isolation method using a LOCOS (Local Oxidation of Silicon)-based selective oxidation technology is adopted for an isolation to define active region
480
. However, in the isolation method using the LOCOS-based selective oxidation technology, a reduction in the active region due to a beak-shaped spread of an oxidized film, which is called a bird's beak, is caused. In manufacturing processes according to a design rule of 0.18 &mgr;m which corresponds to a DRAM class having a storage capacity of 1 giga bit, this bird's beak is a problem, and an edge of the pattern of active region
480
shown in
FIG. 3
is narrowed.
More specifically described, since both ends of active region
480
are close to an activation region (another active region
480
), it is impossible to widen an effective area of active region
480
after a selective oxidation, in so far as an area of the memory cell is not enlarged. For this reason, lower capacitor electrode contact
487
provided on active region
480
shown in
FIG. 2B
is not opened on active region
480
, and an unsatisfactory conduction between lower capacitor electrode
488
and active region
480
may occur.
With respect to not only working for making the configuration of the memory cell but also an electric characteristic thereof, the isolation in the memory cell is insufficient by LOCOS-based isolation, so that the LOCOS-based isolation can not be applied to a DRAM in the 0.18 &mgr;m rule class.
As isolation method in such class, it has been known that a trench isolation is suitably adopted. However, the pattern of active region
480
shown in
FIG. 3
takes a layout in which a wide separation space portion and a narrow separation space portion mixedly exist.
In such pattern layout, when an oxide film formed by a CVD method is filled also in a trench, which is formed by etching a silicon substrate, in order to form a trench isolation region, a problem occurs that although the wide isolation space portion is filled with the oxide film, the narrow isolation space portion is not perfectly filled with the oxide film. In other words, a gap portion in which the oxide film is not filled is produced in the narrow isolation portion.
Furthermore, when such trench isolation is applied to manufacture the memory cell, a memory cell for preventing the burying problem described above has been proposed. Hereinafter, a conventional layout for the memory cell will be described, in which it is tried to solve the burying problem by making the trench widths uniform in the memory cell. This is an example disclosed in IEDM, Technical Digest, pp 903-906, 1995.
FIG. 4
shows a pattern layout of the memory cell array portion of this example in which active region
280
, word line
284
, source/drain region
290
a
,
290
b
, and
290
c
are illustrated in the central region. When attention is paid to this active region
280
, an interval between the active regions, that is, an interval to isolate the active regions, is seen to be constant. Therefore, as long as the foregoing arguments is considered from view of this point, the problem that the gap due to lack of uniformity of the foregoing isolation interval occurs in the buried oxide film for the trench isolation is removed.
However,
FIG. 4
shows the example in which word line
284
is formed out of position with respect to active region
280
. As is understood from this drawing, another problem occurs in such pattern layout. Specifically, slanted lines are partially drawn among source/drain regions
290
a
,
290
b
and
290
c
, and source/drain regions of switching transistors to be paired with each other are source/drain regions
290
a
and
290
c
, for source/drain region
290
b
which is connected with bit line contact
286
. One switching transistor is composed of source/drain region
290
a
and source/drain region
290
b
, and another switching transistor is composed of source/drain region
290
b
and source/drain region
290
c
. With reference to channel widths of these two paired switching transistors, one of the channel widths is determined depending on a wider width portion of source/drain region
290
b
. The other is apparently equal to a thin portion of the channel of source/drain region
290
b
. Therefore, characteristics of the paired switching transistors are made to be unbalanced owing to a difference between the channel widths thereof.
In addition to the foregoing examples, there is an example of a layout pattern, disclosed in IEDM, Technical Digest, pp. 297-299, 1994, in which the interval of the isolation regions are made to be uniform, thus allowing them to avoid the burying problem of a isolation oxide film.
FIG. 5
shows a layout pattern of the memory cell array portion of this example, in which active region
380
, word line
384
and source/drain regions
390
a
,
390
b
and
390
c
are drawn as main subjects. In this active region
380
, an interval of an isolation is constant. Furthermore, in
FIG. 5
, slanted lines are drawn in the source/drain region constituting the paired switching transistors as in the foregoing example, and also in this example the layout is incapable of avoiding the unbalance of the characteristics of the p
NEC Corporation
Nguyen Cuong Quang
Sughrue Mion Zinn Macpeak & Seas, PLLC
Thomas Tom
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