Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-12
2001-08-14
Nelms, David (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C365S185270
Reexamination Certificate
active
06275972
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to integrated circuit (IC) devices. More particularly, the present invention relates to a method for accurate channel-length extraction or measurement in metal oxide semiconductor field effect transistors (MOSFETs).
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally built on the top surface of a bulk substrate. The substrate is doped to form impurity diffusion layers (i.e. source and drain regions). A conductive layer is situated between the source and drain regions; the conductive layer operates as a gate for the transistor. The gate controls current in a channel between the source and the drain regions.
Accurate determination of the effective channel length becomes ever more important for device miniaturization, optimization, and modeling. Conventional efforts to find a simple and accurate method to determine or extract the channel length of a MOSFET device are based upon measurements of resistance, capacitance, and interface states. However, in order to use capacitance and interface related methods, higher resolution equipment is required to measure gate capacitance in the range of femto (10
−15
) farads and detect substrate current down to the level of pico (10
−12
) amperes, especially as gate lengths approach distances of less than 70 nm. As such, capacitance and interface related methods are not recommended for routine monitoring in a mass production environment.
Compared to capacitance and interface related methods, channel length extraction algorithms based on resistance are much simpler. Resistance related methods such as “paired V
G
(gate voltage)” and “shift and ratio” are used conventionally in practical applications. Nevertheless, the charge sharing effect by the source/drain depletion, gate bias dependence of the source/drain resistance, and the non-linearity problem inherent to proper calculation of V
T
(threshold voltage) make accurate determination of deep sub-micrometer channel length difficult using resistance related methods.
Thus, there is a need for a method for accurate channel-length extraction. Further, there is a need for a method of accurate channel-length extraction for use in mass IC fabrication processes. Even further, there is a need for a simple and accurate measurement of transistor channel length.
SUMMARY OF THE INVENTION
One embodiment of the invention relates to a method for extracting a channel length between a source and a drain in a substrate of a transistor. The method includes forward biasing the source with respect to the substrate to inject a charge into the substrate, collecting the charge at the drain, and calculating the channel length from the charge collected at the drain.
Another embodiment of the invention relates to an apparatus for extracting a channel length between a source and a drain in a substrate of a transistor. The apparatus includes means for forward biasing the source with respect to the substrate to inject a charge into the substrate, means for collecting the charge at the drain, and means for calculating the channel length from the charge collected at the drain.
Another embodiment of the invention relates to a system for extracting a channel length between a source region and a drain region in a substrate of a transistor. The system includes a voltage source, a current collector, and a processing unit. The voltage source is coupled to the source region and injects a charge into the substrate. The current collector is coupled to the drain region and collects the charge from the substrate received by the drain region. The processing unit determines the channel length from the charge collected by the current collector.
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Liu Yowjuang W.
Long Wei
Advanced Micro Devices , Inc.
Foley & Lardner
Le Thong
Nelms David
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