Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-01-09
2001-09-11
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S723000, C438S725000
Reexamination Certificate
active
06287973
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming an interconnection structure in a semiconductor integrated circuit.
As the number of devices, integrated within a single semiconductor integrated circuit, has been tremendously increasing these days, wiring delay has also been increasing noticeably. This is because the larger the number of devices integrated, the larger line-to-line capacitance (i.e., parasitic capacitance between metal interconnects), thus interfering with the performance improvement of a semiconductor integrated circuit. The wiring delay is so-called “RC delay”, which is proportional to the product of the resistance of metal interconnection and the line-to-line capacitance.
In other words, to reduce the wiring delay, either the resistance of metal interconnection or the line-to-line capacitance should be reduced.
In order to reduce the interconnection resistance, IBM Corp., Motorola, Inc., etc. have reported semiconductor integrated circuits using copper, not aluminum alloy, as a material for metal interconnects. A copper material has a specific resistance about two-thirds as high as that of an aluminum alloy material. Accordingly, in accordance with simple calculation, the wiring delay involved with the use of a copper material for metal interconnects can be about two-thirds of that involved with the use of an aluminum alloy material therefor. That is to say, the operating speed can be increased by about 1.5 times.
However, the number of devices, integrated within a single semiconductor integrated circuit, is expected to further increase by leaps and bounds from now on, thus increasing the wiring delay considerably. Therefore, it is concerned that even the use of copper as an alternate metal interconnection material would not be able to catch up with such drastic increase. Also, the specific resistance of copper as a metal interconnection material is just a little bit higher than, but almost equal to, that of gold or silver. Accordingly, even if gold or silver is used instead of copper as a metal interconnection material, the wiring delay can be reduced only slightly.
Under these circumstances, not only reducing interconnection resistance but also suppressing line-to-line capacitance play a key role in further increasing the number of devices that can be integrated within a single semiconductor integrated circuit. And the relative dielectric constant of an interlevel insulating film should be reduced to suppress the line-to-line capacitance. A silicon dioxide film has heretofore been used as a typical material for an interlevel insulating film. The relative dielectric constant of a silicon dioxide film is, however, about 4 to about 4.5. Thus, it would be difficult to apply a silicon dioxide film to a semiconductor integrated circuit incorporating an even larger number of devices.
In order to solve such a problem, fluorine-doped silicon dioxide film, low-dielectric-constant spin-on-glass (SOG) film, organic polymer film and so on have been proposed as alternate interlevel insulating films with respective relative dielectric constants smaller than that of a silicon dioxide film.
The relative dielectric constant of a fluorine-doped silicon dioxide film is about 3.3 to about 3.7, which is about 20 percent lower than that of a conventional silicon dioxide film. Nevertheless, a fluorine-doped silicon dioxide film is highly hygroscopic, and easily absorbs water in the air, resulting in various problems in practice. For example, when the fluorine-doped silicon dioxide film absorbs water, SiOH groups, having a high relative dielectric constant, are introduced into the film. As a result, the relative dielectric constant of the fluorine-doped silicon dioxide film adversely increases, or the SiOH groups react with the water during a heat treatment to release H
2
O gas. In addition, fluorine free radicals, contained in the fluorine-doped silicon dioxide film, segregate near the surface thereof during a heat treatment and react with Ti, contained in a TiN layer formed thereon as an adhesion layer, to form a TiF film, which easily peels off.
An HSQ (hydrogen silsesquioxane) film, composed of Si, O and H atoms, is an exemplary low-dielectric-constant SOG film. In the HSQ film, the number of the H atoms is about two-thirds of that of the O atoms. However, the HSQ film releases a larger amount of water than a conventional silicon dioxide film. Accordingly, since it is difficult to form a buried interconnection line in the HSQ film, a patterned metal film should be formed as metal interconnects on the HSQ film.
Also, since the HSQ film cannot adhere so strongly to metal interconnects, a CVD oxide film should be formed between the metal interconnects and the HSQ film to improve the adhesion therebetween. However, in such a case, if the CVD oxide film is formed on the metal interconnects, then the substantial line-to-line capacitance is equal to the serial capacitance formed by the HSQ and CVD films. This is because the CVD oxide film with a high dielectric constant exists between the metal interconnects. Accordingly, the resulting line-to-line capacitance is larger as compared with using the HSQ film alone.
An organic polymer film, as well as the low-dielectric-constant SOG film, cannot adhere strongly to metal interconnects, either. Accordingly, a CVD oxide film should be formed as an adhesion layer between the metal interconnects and the organic polymer film, too.
Moreover, an etch rate, at which an organic polymer film is etched, is approximately equal to an ash rate, at which a resist pattern is ashed with oxygen plasma. Accordingly, a usual resist application process is not applicable in such a situation, because the organic polymer film is likely to be damaged during ashing and removing the resist pattern. Therefore, a proposed alternate process includes: forming a CVD oxide film on an organic polymer film; forming a resist film on the CVD oxide film; and then etching the resist film using the CVD oxide film as an etch stopper, or a protective film.
However, during the step of forming the CVD oxide film on the organic polymer film, the surface of the organic polymer film is exposed to a reactive gas containing oxygen. Accordingly, the organic polymer film reacts with oxygen to take in polar groups such as carbonyl groups and ketone groups. As a result, the relative dielectric constant of the organic polymer film disadvantageously increases.
Also, in forming inlaid copper interconnects in the organic polymer film, a TIN adhesion layer, for example, should be formed around wiring grooves formed in the organic polymer film, because the organic polymer film cannot adhere strongly to the metal interconnects. However, since the TiN film has a high resistance, the effective cross-sectional area of the metal interconnects decreases. Consecuently, the intended effect attainable by the use of the copper lines, i.e., reduction in resistance, would be lost.
SUMMARY OF THE INVENTION
An object of the present invention is providing a method for forming an interconnection structure in which an insulating film with a low dielectric constant can be formed by an ordinary resist application process.
A first method for forming an interconnection structure according to the present invention includes the steps of: a) forming a first insulating film over lower-level metal interconnects; b) forming a second insulating film, having a different composition than that of the first insulating film, over the first insulating film; c) forming a third insulating film, having a different composition than that of the second insulating film, over the second insulating film; d) forming a thin film over the third insulating film; e) forming a first resist pattern, having a plurality of openings for forming wiring grooves, on the thin film; f) etching the thin film using the first resist pattern as a mask, thereby forming a mask pattern out of the thin film to have the openings for forming wiring grooves; g) forming a second resist pattern, having a plurality of openings for fo
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Robinson Eric J.
Umez-Eronini Lynette T.
Utech Benjamin L.
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