Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1998-07-21
2001-06-05
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S052000, C710S053000
Reexamination Certificate
active
06243770
ABSTRACT:
TECHNICAL FIELD
The present invention relates to communications within a computer. In particular, the present invention relates to the use of multiple interlocking first-in, first-out (“FIFO”) buffers.
BACKGROUND
Using a PCI bus, data transfers can be accomplished using burst transfers. There are two participates in every PCI burst transfer: the initiator and the target. The initiator is the device that initiates the transfer. The target is the device currently addressed by the initiator for the purpose of performing a data transfer. All PCI bus transactions consist of an address phase followed by one or more data phases. During the address phase, the initiator identifies the target device and the type of transaction. The data phase of a transaction is a period during which a data object is transferred between the initiator and the target. The number of data bytes to be transferred during a data phase is determined by the number of Command/Byte Enable signals that are asserted by the initiator during the data phase. Also, the number of data phases depends on how many data transfers are to take place during the overall burst transfer. Each data phase has a minimum duration of one PCI CLK. Each wait state inserted in a data phase extends it by an additional PCI CLK. The duration of a transaction is from the start of the address phase to the completion of the final data phase.
A non-pipelined bus architecture allows only a single transaction at a time, generally consisting of a request (address) phase and a response (data) phase with each response phase completing before the next address phase. A pipelined bus architecture allows multiple outstanding transaction requests (address phases) to be made prior to the completion of subsequent phases. Only one address phase may be active at one time, but there may be multiple address phases that have occurred prior to the corresponding data phases.
Currently, separate FIFO buffers are used in the implementation of a pipelined bus architecture. For instance, an implementation of a pipelined bus architecture may involve having one FIFO buffer for the address phase and one FIFO buffer for the data phase. Three of the problems faced in implementing a pipelined bus architecture having separate FIFO buffers are data overflow, data underflow, and inefficient use of memory. When implementing a pipelined bus architecture with FIFO buffers, multiple addresses may have to be written into the address FIFO buffer prior to having the corresponding data available for writing into the data FIFO buffer. However, in order to prevent data overflow that causes data to be overwritten, there must be space available in the data FIFO buffer prior to accepting an additional address into the address FIFO buffer.
Similarly, for a read operation, multiple addresses may be read from an address FIFO buffer prior to reading the corresponding data from the data FIFO buffer. In order to prevent data underflow (i.e., not having the data available for the addresses that have been read), the data corresponding to the addresses read from the address FIFO buffer must have been written into the data FIFO buffer prior to the addresses being read from the address FIFO buffer. Clearly, a FIFO buffer structure for use in a pipelined bus architecture that will prevent data underflow and data overflow would be desirable.
In implementing a pipelined bus interface, a logic state machine may be used. The logic state machine is responsible for tracking each transaction through its corresponding phase. A problem with using a logic state machine in this manner is that the machine needs to know not only the position of the read and write pointers of its corresponding FIFO buffer, but the position of the read and write pointers of other interrelated FIFO buffers in order to make decisions about the current phase. However, the logic state machine cannot determine the position or location of the pointers within the other interrelated FIFO buffers.
Implementing a pipelined bus to bus interface using separate FIFO buffers may increase storage requirements. Each phase may require access to the same data structure. For instance, such is the case when a snoop phase requires the address to present to the snooping agent and a request phase also requires the same address to present to the request agent. Using separate FIFO buffers for each phase requires storing the same information in two separate data structures. This multiple storage of the same information is an inefficient use of memory. Clearly, a FIFO buffer structure for use in a pipelined bus architecture that reduces storage requirements would be desirable.
SUMMARY
One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.
Another embodiment of the present invention relates to a method for identifying a status of a buffer structure having at least two first-in first-out (“FIFO”) buffers that are interlocked, with each FIFO buffer having a read pointer and a write pointer. The method comprises receiving a logic signal (i.e., a strobe) requesting the performance of an operation on the buffer structure and determining the status of the buffer structure based on the position of at least one pointer of each of the at least two FIFO buffers.
REFERENCES:
patent: 4677616 (1987-06-01), Franklin
patent: 4785415 (1988-11-01), Karlquist
patent: 4814762 (1989-03-01), Franaszek
patent: 5163157 (1992-11-01), Yamano et al.
patent: 5371849 (1994-12-01), Peaslee et al.
patent: 5404480 (1995-04-01), Suzuki
patent: 5444658 (1995-08-01), Izawa et al.
patent: 5680564 (1997-10-01), Divivier et al.
patent: 08191312 (1996-07-01), None
Dorsey & Whitney LLP
Du Thuan
Lee Thomas
Micro)n Technology, Inc.
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