Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
1999-04-06
2001-06-12
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S443000, C438S452000
Reexamination Certificate
active
06245644
ABSTRACT:
BACKGROUND OF THE INVENTION
Integrated circuits are typically fabricated over a semiconductive substrate and can include many individual transistor or device constructions. Implementing electrical circuits involves connecting isolated devices through specific electrical paths. It must, therefore, be possible to isolate respective transistor or device constructions. A variety of techniques have been developed to isolate devices in integrated circuits. One technique, termed LOCOS isolation (for LOCal Oxidation of Silicon) involves the formation of a semi-recessed oxide in the nonactive (or field) areas of the substrate. Prior art LOCOS isolation is discussed briefly in this section as such pertains to the present invention. For a more detailed discussion of LOCOS isolation, the reader is directed to a text by Wolf entitled, “Silicon Processing for the VLSI Era”, Vol. 2, Chapter 2, the disclosure of which is hereby incorporated by reference.
Referring to
FIG. 1
, a prior art semiconductor wafer fragment in process is indicated generally by reference numeral
10
. Such comprises a semiconductive substrate
12
over which a field oxide or isolation oxide region is to be formed by LOCOS techniques. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to bulk semiconductive material such as semiconductive wafer (either alone or in assemblies comprising other materials thereon) and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. A pad oxide layer
14
is formed over substrate
12
and an oxidation mask
16
, comprised of a suitable material such as silicon nitride, is formed over pad oxide layer
14
. Portions of layers
14
,
16
(not shown) have been removed to expose a substrate portion
18
. Portion
18
constitutes a portion of the substrate in which a LOCOS isolation structure or isolation oxide region is to be formed. Adjacent substrate portion
18
, a masked substrate portion
20
remains. Portion
20
constitutes at least a portion of the substrate which is to support at least one integrated circuit construction. Accordingly, such portion constitutes an active area.
Referring to
FIG. 2
, substrate
12
is exposed to oxidation conditions which are sufficient to form oxide isolation region or field oxide region
22
within portion
18
. Accordingly, as is known, the formation of region
22
typically causes a bird's beak region
24
to be formed, a portion of which extends under and upwardly lifts oxidation mask
16
.
Referring to
FIG. 3
, oxidation mask
16
and pad oxide layer
14
are suitably removed or etched. Such defines a more pronounced bird's beak in region
24
.
Referring to
FIG. 4
, a sacrificial oxide layer
26
is formed over substrate
12
typically to overcome a phenomena known as the Kooi effect. During the growth of field oxide, the Kooi effect can cause later defects when a gate oxide is formed. More specifically, during field oxide growth, a thin layer of silicon nitride can form on the silicon surface and close to the border of the active regions as a result of the reaction between the oxidizing species, oxygen and water, and the silicon nitride. In particular, NH
3
is generated from the reaction between the water and the masking nitride during the field oxidation step. This NH
3
then diffuses through the oxide and reacts with the silicon substrate to form silicon-nitride ribbons. When the nitride mask and pad oxide are removed, there is a possibility that the silicon-nitride ribbon remains present. When gate oxide is subsequently grown, the growth rate becomes impeded at the locations where such silicon-nitride ribbons remain. The gate oxide is thus thinner at these locations than elsewhere giving rise to problems associated to low voltage breakdown of the gate oxide. The most widely used method of eliminating the silicon-nitride ribbon problem is to grow a sacrificial oxide layer, typically about 25 to about 50 nanometers thick, after stripping the masking nitride and pad oxide. This sacrificial oxide layer is then removed by wet etching before growing the final gate oxide.
It has been found that the removal of the prior formed pad oxide layer
14
(
FIG. 2
) together with the formation and removal of the sacrificial oxide layer
26
can lead to a slightly thinner region
28
adjacent oxide isolation region
22
when the gate oxide layer is ultimately formed.
Referring to
FIG. 5
, and prior to formation of a gate oxide layer, sacrificial oxide layer
26
is suitably removed. In the illustrated example, such can cause field oxide region
22
to be recessed to a degree which results in the formation of a convex bump
30
laterally adjacent oxide isolation region
22
.
Referring to
FIG. 6
, a gate oxide layer
32
is formed over substrate
12
. Oxidation of bump
30
results in localized thinning of the gate oxide within region
28
. Such thinning can lead to device failure brought on by gate shorting.
This invention arose out of concerns associated with improving the processing of semiconductor devices. This invention also arose out of concerns associated with improving the uniformity with which semiconductor devices can be formed.
SUMMARY OF THE INVENTION
Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material. During the filling of the undercut region, at least some of the mass or spacer is oxidized to form a bump over the bird's beak region. Oxide material is then removed from over the active area with such removal reducing the size of the bump. A gate dielectric layer can then be provided over the active area.
REFERENCES:
patent: 4219379 (1980-08-01), Athanas
patent: 4407696 (1983-10-01), Han et al.
patent: 4539744 (1985-09-01), Burton
patent: 4679304 (1987-07-01), Bois
patent: 4952525 (1990-08-01), Van Der Plas
patent: 5175123 (1992-12-01), Vasquez et al.
patent: 5432117 (1995-07-01), Yamamoto
patent: 5930647 (1999-07-01), Mathews
Silicon Processingfor the VLSI Era, S. Wolf, vol. 2, Chap. 2.
Bowers Charles
Hawranek Scott J.
Micro)n Technology, Inc.
Wells, St. John, Roberts Gregory & Matkin P.S.
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