Dual damascene process for manufacturing interconnects

Details Dual damascene process for manufacturing interconnects Dual damascene process for manufacturing interconnects

1999-05-25

2001-04-03

Loke, Steven (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S622000, C438S629000, C438S636000, C438S637000, C438S638000, C438S640000, C257S750000, C257S751000, C257S752000, C257S753000, C257S758000, C257S774000

Reexamination Certificate

active

06211068

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing interconnects. More particularly, the present invention relates to a method for manufacturing interconnects using a dual damascene process.
2. Description of Related Art
In the fabrication of very large scale integrated (VLSI) circuits, semiconductor devices are generally linked by several metallic interconnecting layers commonly referred to as multilevel interconnects. As the level of circuit integration continues to increase, manufacturing processes are complicated and product yield and reliability is harder to maintain. Dual damascene process is a convenient method for forming multilevel interconnects. Principally, the process includes etching a dielectric layer to form trenches, and then depositing metal into the trenches to form the interconnects. The dual damascene process is capable of producing highly reliable interconnects with a relatively high product yield. Due to its versatility, the dual damascene process has become a predominant method for fabricating interconnects. However, several drawbacks in the method still need to be resolved. For example, photoresist (PR) that remains inside a via hole after a photolithographic operation may affect the profile of the via hole.
FIGS. 1A through 1C
are schematic, cross-sectional views showing the steps taken in carrying out a conventional dual damascene process for fabricating interconnects. As shown in
FIG. 1A
, a semiconductor substrate
100
having a metallic layer
102
therein is provided. A silicon nitride layer
104
having a thickness of about 500 Å to 1000 Å is formed over the substrate
100
. An inter-layer dielectric layer
106
having a thickness of about 9000 Å to 16000 Å is formed over the silicon nitride layer
104
. A patterned photoresist layer
108
is formed over the inter-layer dielectric layer
106
using photolithographic techniques. Using the patterned photoresist layer
108
as a mask, the dielectric layer
106
is etched to form a via hole
110
.
As shown in
FIG. 1B
, the photoresist layer
108
is removed. Meanwhile, another photoresist layer
112
to define the metal trench is formed over the inter-layer dielectric
106
. Some of the photoresist material is also deposited into the via hole
110
. The photoresist layer
112
is patterned by removing some photoresist material. However, some photoresist material inside the via hole
110
remains and forms a residual photoresist layer
112
a.
As shown in
FIG. 1C
, using the photoresist layer
112
as a mask, an anisotropic etching operation is conducted to form trenches
114
inside the inter-layer dielectric
106
. Subsequent processing steps are not shown in the figure because those steps should be familiar to the people in the semiconductor field. In brief, subsequent steps includes the removal of the photoresist layer
112
, deposition to form a barrier layer and a copper layer and a final planarization using a chemical-mechanical polishing (CMP) method.
As shown in
FIG. 1C
, due to the difficulties in removing away some of the dielectric material in the neighborhood of the residual photoresist
112
a
, an undesirable trench profile is often created. In addition, the dielectric layer
106
is typically a silicon dioxide layer, which is a transparent material. Therefore, an anti-reflection coating is frequently required. However, the formation of the silicon nitride layer
104
as an anti-reflection coating between the metallic layer
102
and the dielectric layer
106
is far from ideal.
SUMMARY OF THE INVENTION
The invention provides a method of forming a dual damascene structure including the formation of a silicon oxynitride layer over an inter-layer dielectric layer that acts as an anti-reflection coating. The additional anti-reflection coating is able to improve the resulting trench profile after the trench-etching step. Furthermore, a portion of the photoresist material inside via holes is removed before carrying out the trench-forming etching operation. Hence, the photoresist layer inside the via hole no longer impedes the etching of dielectric material around the via hole/contact opening areas as in a conventional dual damascene process.
The invention provides a dual damascene process for producing interconnects. The dual damascene process includes forming an etching stop layer over a substrate having a conductive layer therein, and forming an inter-layer dielectric layer over the etching stop layer. A mask layer is formed over the dielectric layer. The mask layer and the inter-layer dielectric layer are patterned to form an opening that exposes a portion of the etching stop layer. The opening is formed above the conductive layer. Photoresist material is deposited over the mask layer and into the opening. The photoresist layer and the mask layer are patterned. After patterning, some of the photoresist may remain in the opening and form a photoresist plug at the same time. A top layer of the photoresist plug is removed. Using the patterned photoresist layer and the mask layer as a mask, an anisotropic etching step is carried out to form a plurality of trenches inside the inter-layer dielectric layer. These trenches overlap with the opening. Metal is finally deposited into the opening and the trenches to complete the dual damascene process.


REFERENCES:
patent: 5529953 (1996-06-01), Shoda
patent: 5689140 (1997-11-01), Shoda
patent: 5702982 (1997-12-01), Lee et al.
patent: 5726100 (1998-03-01), Givens
patent: 5877076 (1999-03-01), Dai
patent: 5882996 (1999-03-01), Dai
patent: 5969422 (1999-10-01), Ting et al.
patent: 5981377 (1999-11-01), Koyama
patent: 6008119 (1999-12-01), Fournier
patent: 6016000 (2000-01-01), Moslehi
patent: 6037213 (2000-03-01), Shih et al.
patent: 6042999 (2000-03-01), Lin et al.
patent: 6048787 (2000-04-01), Lee

Affiliated with

Also associated with

Rating

Dual damascene process for manufacturing interconnects does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dual damascene process for manufacturing interconnects, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dual damascene process for manufacturing interconnects will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2456643