Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-04
2001-08-21
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06278146
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric capacitor, more specifically, a ferroelectric capacitor which has improved ferroelectricity.
2. Description of the Prior Art
A conventional ferroelectric capacitor is shown in
FIG. 1. A
silicon oxide layer
4
is formed on a silicon substrate
2
, then a lower electrode
6
made of platinum is formed thereon. A PZT (PbZr
x
Ti
1-x
O
3
) layer
8
as a ferroelectric layer is formed on the lower layer
6
. Further, an upper layer
10
made of platinum is formed thereon. So that, a ferroelectric capacitor is formed by the lower electrode
6
, the PZT layer
8
and the upper electrode
10
.
The reason why the lower electrode
6
is made by platinum is as follows. The PZT layer
8
must be formed on a layer which is oriented axially or which has monocrystal for obtaining better matching of lattice constant. When the PZT layer
8
is formed on an amorphous layer, ferroelectricity of the PZT layer is decreased because the amorphous layer is a layer which is not oriented axially. On the other hand, the lower electrode
6
must be formed under insulated condition from the silicon substrate
2
. Because of this, the silicon oxide layer
4
is formed on the silicon substrate
2
. Also the silicon oxide layer
4
is amorphous. Generally, a layer formed on amorphous material becomes a layer which is not oriented axially. However, platinum has characteristics that become a layer which is oriented axially even when it is formed on amorphous material. Therefore, platinum is utilized for the lower electrode
6
.
FIG. 3A
illustrates a structure of a memory device which is proposed by using a ferroelectric capacitor. A source region
104
and a drain region
106
are formed in the silicon substrate
102
, a gate electrode
108
is formed on the channel region. A plug
110
made of poly silicon is formed on the drain region
106
of this transistor structure. Further, a platinum layer
112
is formed on the poly silicon plug
110
, also PZT layer
114
is formed thereon as ferroelectric material. Further, a platinum layer
116
is formed on the PZT layer
114
. From this, the memory device is formed.
Because the manufacturing process of PZT is totally different from that of a transistor, the platinum layer
112
, PZT layer
114
, and the platinum layer
116
are formed on the poly silicon plug
110
as shown in the figure.
The conventional ferroelectric capacitor shown in
FIG. 1
has the following issues to resolve. At first, depending on kind and composition of the ferroelectric material, a possibility of mismatching lattice constant between the ferroelectric material and the platinum layer formed as the lower electrode is increased, so that ferroelectricity of the capacitor is possibly degraded.
Subsequently, platinum has characteristics that oxygen goes though it easily, so that oxygen contained in the ferroelectric material (such as PZT) leaks therefrom. Therefore, degradation for retention property and fatigue property besides repeated polarization reverse is caused. That is, oxygen contained in the ferroelectric material leaks through columnar crystal structure of platinum as shown in FIG.
2
.
It is necessary to resolve the following issues to realize a conventional memory device shown in FIG.
3
A.
In
FIG. 3A
, the platinum layer
112
is formed directly on the poly silicon plug
110
. This way, platinum and poly silicon react chemically, forming silicide. Once silicide is formed, it is not possible to obtain high ferroelectricity. Even if a ferroelectric layer is formed thereon, the lattice constant between silicide and the ferroelectric layer is totally different from each other. Also, since the surface of the poly silicon plug
110
has roughness, platinum formed on the poly silicon plug
110
can not be oriented. Therefore, the ferroelectric layer formed thereon does not have high ferroelectricity.
FIG. 3B
shows a hysteresis curve of PZT formed on platinum which is formed on poly silicon. As it is clear from the figure, remanent polarization Pr is almost disappeared from the figure. The same issue is observed when tungsten is used as the plug.
To resolve above described problems, there is a case that a tantalum layer which does not react with the platinum layer
112
is formed on the poly silicon plug
110
, then the platinum layer
112
is formed thereon. According to above way, it is possible to prevent forming polycide as a result of chemical reaction of platinum and poly silicon, also better ferroelectricity can be observed due to improvement of orientation for the ferroelectric layer. However, the surface of the tantalum layer
113
maintains roughness of the surface of the poly silicon plug
110
, as shown in FIG.
4
A. Therefore, platinum formed thereon can not be oriented axially. Then, the ferroelectric layer formed on the platinum does not have high ferroelectricity. Also, there is an issue that tantalum oxide is formed in a boundary between the poly silicon plug
110
and the tantalum layer
113
caused by thermal treatment. Therefore, the dielectric constant of the memory device is decreased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a ferroelectric capacitor which realizes less degradation for retention property and fatigue property besides repeated polarization reverse.
Also, another object of the present invention is to provide a ferroelectric capacitor which maintains high ferroelectricity, less degradation for retention property, fatigue property and repeated polarization reverse.
Yet another object of the present invention is to provide a dielectric capacitor and memory device having excellent characteristics.
A ferroelectric capacitor comprises:
a) a substrate of semiconductor;
b) a lower electrode located on the substrate of semiconductor, having an alloy layer made of platinum and iridium;
c) a ferroelectric layer formed on the lower electrode contacting with the alloy layer of the lower electrode;
d) an upper electrode formed on the ferroelectric layer.
While the novel features of the invention are set forth in a general fashion, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings.
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Loke Steven
Merchant & Gould P.C.
Nguyen Cuong Q
Rohm & Co., Ltd.
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