Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-08
2001-04-10
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S700000, C438S639000, C438S640000
Reexamination Certificate
active
06214715
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a two step process for forming spacers in a self aligned contact process which eliminates the key hole problem in the IPO (inter-poly oxide) layer.
2) Description of the Prior Art
The use of self aligned contact (SAC) processes has resulted in higher performing, lower cost, and increased density semiconductor devices. A self aligned contact process spacers are formed on the sidewalls of conductive structures (such as gates and bit lines); and IPO layer is formed over these conductive structures; a contact opening is etched through the IPO; and a conductive layer is formed over the conductive structures and in the contact opening. However, as device dimensions and die sizes continue to decrease for higher density, the space between adjacent conductive structures becomes narrower. The surface of the sidewall spacers facing the contact opening become concave (overhang) which leads to voids or key holes in the subsequently formed IPO layer. The key holes can cause two separate devices (such as capacitors) which are formed over the IPO layer to short, resulting in cell failure.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,747,373 (Yu) shows a method of forming a first SiN spacer and a second oxide spacer.
U.S. Pat. No. 5,208,472 (Su et al.) shows a double dielectric spacer. The first is oxide and the second is of a dielectric material.
U.S. Pat. No. 5,827,782 (Shih) shows a method of optimizing an IMD spacer layer profile.
U.S. Pat. No. 5,789,314 (Yen et al.) shows an IMD layer method with an etchback of an oxide layer.
U.S. Pat. No. 5,296,092 (Kim) teaches a planarization method where an upper portion of the oxide layer is etched back.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a self aligned contact using a two-step spacer deposition.
It is another object of the present invention to provide a method for forming a self aligned contact which avoids the key hole problem by improving the sidewall spacer profile using a two-step spacer deposition.
It is another object of the present invention to provide a method for forming a self aligned contact which avoids capacitor crown to crown shorting by using a two-step spacer deposition.
It is yet another object of the present invention to provide a method for forming a self aligned contact using a two-step spacer deposition which is easy to integrate with current processes.
To accomplish the above objectives, the present invention provides a method for forming a self aligned contact without key holes using a two step sidewall spacer deposition. The process begins by providing a semiconductor structure having a first device layer over the semiconductor structure, a first inter-polysilicon oxide layer (IPO-
1
) over the first device layer, and a conductive structure (such as a bit line) with sidewalls on the IPO-
1
layer and having a contact area on the semiconductor structure adjacent to the conductive structure. The conductive structure comprises at least one conductive layer with a hard mask thereover. A thin first spacer layer is formed over the hard mask and the semiconductor structure and anisotropically etched to form first sidewall spacers having a profile that is not concave at any point on the sidewalls of the conductive structure up to a level above the bottom of the hard mask and below the level of the top of the hard mask. A second spacer layer is formed over the first sidewall spacers and anisotropically etched to form second sidewall spacers, having a profile that is not concave at any point. A second inter poly oxide layer (IPO-
2
) is formed over the second sidewall spacers, the hard mask, and the semiconductor structure, whereby the IPO-
2
layer is free from key holes. A contact opening is formed in the IPO-
1
layer and the IPO-
2
layer over the contact area. A contact plug is formed in the contact opening.
The present invention provides considerable improvement over the prior art. Most significantly, the profile of the sidewall spacers are controlled so that they do not become concave at any point. Because the first sidewall spacer layer is thinner than a spacer in a single spacer process, a concave (overhead) profile does not form. When the second spacer layer is formed, it is formed over the convex first spacer profile and it also is free from the overhead problem. This profile control prevents the formation of voids or key holes in the subsequently formed IPO-
2
layer.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5208472 (1993-05-01), Su et al.
patent: 5296092 (1994-03-01), Kim
patent: 5405791 (1995-04-01), Ahmad et al.
patent: 5747373 (1998-05-01), Yu
patent: 5789314 (1998-08-01), Yen et al.
patent: 5824588 (1998-10-01), Liu
patent: 5827782 (1998-10-01), Shih
patent: 6040223 (1998-10-01), Liu et al.
Chiang Wen-Chuan
Huang Kuo-Ching
Ying Tse-Liang
Ackerman Stephen B.
Everhart Caridad
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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