Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-22
2001-04-24
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S384000, C257S915000
Reexamination Certificate
active
06222240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a metal oxide gate dielectric and salicide structures from a unitary layer of refractory metal, wherein the salicide structures are self-aligned to a pair of source and drain regions.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After impurity regions have been placed into a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric is formed across the topography to isolate the gate areas and the impurity regions. Interconnect routing is then placed across the semiconductor topography and connected to the impurity regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. The entire process of making ohmic contacts to the impurity regions and/or the gate areas and routing interconnect material between the ohmic contacts is generally described as “metallization”. As the complexity of integrated circuits has increased, the complexity of the metallization composition has also increased. Conductive materials other than metal are commonly used for metallization. As such, the term metallization is generic in its application.
Integrated circuits often employ active devices known as transistors. A transistor includes a pair of impurity regions, i.e., junctions, spaced apart by a gate conductor. A gate dielectric is interposed between the gate conductor and a semiconductor substrate within which the junctions reside. The junctions contain dopants which are opposite in type to the dopants residing within a channel region of the substrate interposed between the junctions. The gate conductor typically comprises polycrystalline silicon (“polysilicon”) which is rendered conductive by implanting dopants therein. Polysilicon can withstand relatively high temperatures. Therefore, a polysilicon gate conductor may be formed prior to performing high-temperature anneal steps, such as the post-implant anneal of the junctions. As such, the gate conductor may be patterned before the source and drain junctions are formed and annealed. In fact, the gate conductor is commonly used as a channel region mask during the formation of the source and drain junctions. One of the disadvantages of using polysilicon as the gate conductor material, however, is that it has a significantly higher resistivity than metals, such as aluminum. The propagation delay of an integrated circuit employing a polysilicon gate conductor thus may be longer than desired.
Capacitive coupling between gate conductors and underlying channel regions of a substrate may be reduced to achieve high-frequency operation of an integrated circuit. Typically, the gate-to-substrate capacitance is decreased by reducing the thickness of the gate dielectric, which is commonly composed of silicon dioxide. However, relatively thin gate dielectrics tend to break down when subjected to an electric field. Electrons may pass through the thin gate dielectric by what is known as the quantum mechanical tunneling effect. As a result, a tunneling current may inadvertently flow between the two conductive layers. It would therefore be of benefit to develop a method for reducing capacitive coupling between the gate conductor and the substrate without decreasing the thickness of the gate dielectric.
The formation of ohmic contacts through an interlevel dielectric involves using a technique known as lithography to pattern a protective mask (i.e., photoresist) upon areas of the dielectric exclusive of where the contacts are to be formed. The areas of the interlevel dielectric left uncovered by the mask are then etched to form openings or “windows” through the interlevel dielectric to underlying junctions and gate conductors. The contact windows are filled with a conductive material to complete formation of the contacts. Unfortunately, the mask may be misaligned relative to the underlying topography during the lithography process. Accordingly, the contacts may be shifted from their targeted positions directly above the junctions and the gate conductors. As a result of the misalignment, the contact/junction and contact/gate conductor interfaces may experience increased contact resistances. The parasitic series resistances of the source and drain contact structures thus may be high enough to detrimentally affect the drive current of transistors employed by the integrated circuit
To reduce the contact resistances at the contact/junction and contact/gate conductor interfaces, self-aligned low resistivity structures are commonly placed between the ohmic contacts and the junctions/gate conductors. The presence of these so-called self-aligned silicides (i.e., salicides) upon the junctions and gate conductors ensures that contact is made to the entire junction and gate areas. Further, forming salicide upon a polysilicon gate conductor helps lower the sheet resistance of the gate conductor. Salicide formed upon polysilicon is generally referred to as polycide. A salicide process involves depositing a refractory metal across the semiconductor topography, and then reacting the metal only in regions where a high concentration of silicon atoms are present. In this manner, salicides may be formed exclusively upon the junctions and the upper surfaces of polysilicon gate conductors. The sidewall surfaces which bound the gate conductors may be pre-disposed with sidewall spacers comprising silicon dioxide (“oxide”). The oxide spacers serve to prevent the refractory metal from contacting, and hence reacting with, the polysilicon at the sidewall surfaces of the gate conductor. Absent the oxide spacers, silicide could form upon the sidewall surfaces of the gate conductors, undesirably shorting the gate conductors to adjacent junctions.
Titanium silicide (TiSi
2
) is attractive for salicide application because it exhibits low resistivity and can withstand process temperatures in excess of 800° C. Formation of a low resistivity TiSi
2
involves annealing a titanium layer placed over silicon at a relatively high temperature. Unfortunately, Ti is highly reactive with SiO
2
when heated to temperatures above 700° C. The relatively weak Si—O bonds of oxide are easily broken, permitting the reaction of Ti with both Si atoms and O atoms. As such, the presence of oxide spacers upon the sidewall surfaces of a gate conductor may not be adequate protection against lateral formation of silicide between the gate conductor and adjacent junctions. Also, titanium oxide may form within the spacers, degrading the integrity of the spacers. It would therefore be desirable to develop a technique for forming salicide upon the junctions of a transistor without being concerned that the junctions might be shorted to the gate conductor.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by the technique hereof for forming a metal oxide gate dielectric and salicide structures from a unitary layer of refractory metal. The refractory metal layer is placed upon a silicon-based substrate before the formation of the gate conductor. A select portion of the refractory metal layer may thus be oxidized to form a relatively thick gate dielectric. The thickness of the gate dielectric is sufficient to prevent the unoxidized portions of the refractory metal layer from contacting the gate conductor. Absent any metal adjacent the sidewall surfaces of the gate conductor, an electrical short cannot be formed between the gate conductor and source and drain junctions arranged on opposite sides of the gate conductor. Further, no oxide sidewall spacers are required to prevent salicidation of the sidewall surfaces of the gate conductor. If oxide sidewall spacers are required for other reasons, they may be formed subsequent to the deposition of the refractory metal layer. As such, no metal atoms, e.g., Ti atoms, are available upon the oxide spacers to react with the SiO
2
to form a metal silicide. Initially depositing the refractory metal lay
Fulford H. Jim
Gardner Mark I.
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Daffer Kevin L.
Prenty Mark V.
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