Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-03-11
2001-03-27
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S712000, C438S714000, C438S721000, C438S724000
Reexamination Certificate
active
06207580
ABSTRACT:
FIELD OF INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits (ICs) and more particularly to an improved method of plasma etching a silicon nitride masked tungsten silicide layer in the gate conductor stack formation that preserves the silicon nitride mask integrity.
BACKGROUND OF THE INVENTION
In the manufacture of advanced semiconductor ICs, particularly in DRAM chips, Insulated Gate Field Effect Transistors (IGFETs) are extensively used.
FIG. 1A
schematically shows a portion of a semiconductor wafer at the initial stage of the gate conductor (GC) stack formation. In
FIG. 1A
, there is shown a conventional semiconductor structure
10
comprising a silicon substrate
11
coated by a thin 10 nm silicon oxide (SiO2) layer
12
(the gate dielectric of the IGFETs) with the GC stack
13
formed thereon. The GC stack
13
typically consists of a plurality of adjacent layers: a bottom 100 nm thick arsenic doped polysilicon layer
14
, a 80 nm thick tungsten silicide (WSix) layer
15
and a 280 nm thick top silicon nitride (Si3N4) layer
16
. The deposition of a refractory metal silicide (e.g. WSix) over a layer of polysilicon is extensively used in the semiconductor industry, forming a composite structure usually referred to as a polycide layer. A photoresist layer
17
is formed over the GC stack
13
as standard. The GC stack
13
delineation process starts with the patterning of the photoresist layer
17
to produce the desired mask. This photoresist mask is used to selectively etch the exposed portions of the underlying Si3N4 top layer
16
. The resulting structure is shown in FIG.
1
B. The photoresist mask
17
is then stripped by ashing in ozone and structure
10
is cleaned as standard. The next step consists in transferring the pattern in the underlying tungsten silicide layer
15
using the Si3N4 top layer
16
as an in-situ hard mask. This step is monitored by an optical etch end point system to detect the WSix/doped polysilicon interface.
A number of chemistries have been developed so far for the elective etching of tungsten silicide with regards to the silicon nitride material of layer
16
. However, only a few employ oxygen as a passivating component to improve etch uniformity. When oxygen is used, it is always with a very low proportion in the etching mixture. For instance, the Applicant used a C12/HCl/O2 chemistry with a LAM TCP 9400 plasma etcher, an equipment sold by LAM Research Corp., Fremont, Calif., USA.
The following operating conditions were:
C12 flow: 40 sccm
HCl flow: 80 sccm
O2 flow : 3 sccm
Pressure: 5 mtorr
RF frequency: 13.56 Mhz
TCP power: 200 W
Bias power: 300 W
wherein “sccm” denotes standard cubic centimeters per minute.
There are two RF generators, one for the TCP (transformer coupled plasma) to increase the plasma density in order to improve etch rate and uniformity and the other one to insure the plasma to be more ionic. In view of the respective gas flows indicated above, the selected ratio is thus in percent: 32.6% C12, 65% HCl and 2.4% 02. The Si3N4:WSix etch selectivity of this mixture is about 2.33:1. As a matter of fact, a very low oxygen percentage is used during this step to improve etch uniformity (micro-loading effects) between nested (or dense) and isolated (or open) areas of the wafer.
This step is very important because it is essential to preserve the thickness and the integrity of the remaining portions of the Si3N4 top layer
16
as it will be discussed in more details hereinafter. In addition, the etching of the doped polysilicon layer
14
is initiated during this step, and it is also very important that the polysilicon etching be anisotropically performed to ensure a straight profile of the of the polysilicon material being etched.
Now, the doped polysilicon layer
14
is etched using a C12/O2 mixture, still in the LAM plasma etcher mentioned above. The composition change aims to increase selectivity between doped polysilicon and SiO2 to preserve gate oxide layer integrity.
The following operating conditions are:
C12 flow: 20 sccm
O2 flow : 3 sccm
Pressure: 5 mtorr
RF frequency: 13.56 Mhz
TCP power: 200 W
Bias power: 50 W
The wafer is cleaned in a DHF solution as standard to remove the SiOx formed on the gate oxide layer
12
during this step. At this stage of the GC stack fabrication process, the structure is shown in FIG.
1
C. As apparent in
FIG. 1C
, the remaining portions of the GC stack
13
have the general shape of lines, referred to hereinbelow as the GC lines and still bearing numeral
13
.
In the above described etch process, the step of etching the tungsten silicide through the Si3N4 top layer
16
that will be subsequently used as an in-situ hard mask is by far the most critical. The C12/HCl/O2 chemistry described above has two major drawbacks. Firstly, it etches in excess the Si3N4 top layer
16
. As a matter of fact, because of the high density plasma and chlorine flow, the Si3N4 top layer thickness is reduced from 280 nm to 250 nm, so that, as apparent in
FIG. 1C
, there is a significant erosion of the original Si3N4 top layer. Secondly, although the GC lines
13
are shown in
FIG. 1C
with a vertical profile, it should be understood that in reality the angle &thgr; defined by the GC line lateral side and the substrate surface is given in TABLE I below. The values (in degrees) are given both for the nested (dense) and the isolated regions of the wafer considering separately the edge and center zones thereof. These values are not satisfactory for the subsequent processing steps.
TABLE I
isolated
nested
edge
85°
86°
center
83°
86°
The GC stack fabrication process continues with the formation of silicon nitride spacers coating the lateral sides of the GC lines
13
. To that end, a 60 nm thick Si3N4 sidewall protection layer is conformally deposited by LPCVD onto the structure
10
and anisotropically etched in an RIE reactor using an optical etch end point system to detect the gate oxide layer exposure. The Si3N4 spacers are referenced
18
in FIG.
1
D.
Now, the structure
10
needs to be planarized. To that end, a 570 nm thick layer
19
of BPSG is blanket deposited by PECVD onto the
FIG. 1D
structure. The BPSG material forming layer
19
has the double role of an insulating and planarizing medium. However, because, the BPSG layer surface is not perfectly planar, a chem-mech polishing step is required to get a mirror-like surface and reduce the BPSG layer thickness to 440 nm. At this stage of the GC stack fabrication process, the resulting structure
10
is shown in FIG.
1
E.
Finally, a photolithographic step is performed in order to define a contact opening
20
through the BPSG layer
19
and the gate oxide layer
12
to expose the silicon substrate
11
prior to source and drain regions formation. To that end, the BPSG layer
19
is etched in a TEL 85 SDRM, a RIE etcher manufactured by TOKYO ELECTRON Lted, Tokyo, JA.
The following operating conditions are adequate:
C4F8 flow: 18 scam
CO flow: 300 scam
Ar flow: 380 scam
Pressure: 57 mtorr
RF frequency: 13.56 Mhz
Bias power: 1400 W
A phosphorous ions implant is then conducted to form said source and drain regions of the IGFETs such as region referenced
21
in FIG.
1
F. Now turning to
FIG. 1F
, the erosion of the Si3N4 layer
16
produced during the WSix etching step, causes some areas of the remaining portions of the WSix layer
15
to be exposed at locations
22
during the contact opening
20
formation. Unfortunately, when during the next step, opening
20
is filled with a metal to define the MO “borderless” contact with region
21
as standard, an electrical short is produced between region
21
and the gate conductor making thereby the corresponding IGFET inoperative.
A GC stack fabrication process limited to the above sequence of steps illustrated by reference to
FIGS. 1A
to
1
C is described in the Int. Appl. published under the PCT No W096/27899, the only noticeable change is that silicon nitride has replaced the SiO2 material as the stack top layer. As a matter of fact, Si3N4 is now preferred bec
Anderson Jay H.
International Business Machines - Corporation
Tran Binh X.
Utech Benjamin L.
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