Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-10-02
2001-03-20
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
06204526
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of capacitors in a dynamic random access memory (DRAM) cell and more particularly to a method and process for fabricating capacitors with a large capacitance.
2) Description of the Prior Art
In dynamic semiconductor memory storage devices, it is essential that storage node capacitor cell plates be large enough to retain an adequate voltage level in spite of parasitic capacitances and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitances is particularly important as the density of DRAM cells continues to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required storage capacitance is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field-effect-transistor (MOS-FET) and a single capacitor, are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 &mgr;m
2
memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta
2
O
5
), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors. In order to increase the surface area of the capacitor, there have also been proposed methods of forming a capacitor with a pin structure extending throughout a multi-layer structure of the capacitor to connect the layers with one another, a method of forming a capacitor using a hemispherical grain polysilicon (HSG) process using polysilicon grains. Also, U.S. Pat. No. 5,447,882 (Kim) shows a related processes for forming a capacitor having a relatively high capacitance. However, many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Therefore, it is very desirable to develop processes that are as simple as possible.
There is a challenge to develop methods of manufacturing the high capacitance capacitors that minimize manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and provides maximum process tolerance to maximize product yields.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a cup shaped capacitor having a high capacitance which uses less photolithographic and etch steps than the conventional processes.
It is an object of the present invention to provide a method for fabricating a cup shaped capacitor having a high density and capacitance, and a self aligned node contact.
It is an object of the present invention to provide a method for fabricating a (DRAM) having capacitor with a high density and capacitance which defines the storage electrode using one mask and two etch steps.
To accomplish the above objectives, the present invention provides a method of manufacturing a cup shaped capacitor for a dynamic random access memory (DRAM) which uses a one masking step and a two step etch process to define the cup shaped storage electrode. Also, the contact node is self aligning. The method begins by providing a MOS (metal oxide semiconductor) device having a gate centered between spaced source and drain regions. An interlayer insulating film is formed over the MOS device and the substrate surface. A first photoresist layer is formed over the interlayer insulating film. The first photoresist layer has a first opening over the source. Next, the interlayer insulating film is isotropically etched through the first opening using the first photoresist layer as a mask forming a cup shaped cavity having sidewalls formed from the interlayer insulating film. Then, the interlayer insulating film is anisotropically etched through the first opening forming a contact hole which exposes the source. The first photoresist layer is then removed. A first conductive layer is then formed over the resulting structure and in the cup shaped cavity and in the node contact hole forming an electrical contact with the source. A top portion of the first conductive layer is removed so that the top surfaces of the first interlayer layer are exposed thus separating adjacent storage electrodes. The interlayer insulating film is removed by a selective etching process thereby forming a cup shaped storage node. Lastly, a dielectric layer and top plate electrode are formed over the bottom storage electrode. The method of defining the cup shaped storage electrode using one masking step and two etch steps produces a capacitor which is closely spaced and uses less masking and etch steps than conventional processes. The invention's one masking step which defines both the contact node and the storage electrode (i.e., aperture), is self aligning, and eliminates at least one mask step thereby making the process cheaper and increasing yields. The saving of one masking step translates into about a 5% savings (4 MB DRAM technology typically has a total of 22 masking layers).
REFERENCES:
patent: 5386382 (1995-01-01), Ahn
patent: 5447882 (1995-09-01), Kim
patent: 5539231 (1996-07-01), Suganaga et al.
Ackerman Stephen B.
Meier Stephen D.
Saile George O.
Stoffel William J.
Vanguard International Semiconductor Corporation
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