Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-07-30
2001-04-24
Smith, Matthew (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C438S128000, C438S400000, C257S618000, C716S030000
Reexamination Certificate
active
06223331
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor circuit design methods, to semiconductor processing methods and to integrated circuitry.
BACKGROUND OF THE INVENTION
Fabrication of integrated circuitry typically involves patterning and etching materials to form substrate features such as conductive lines. In many integrated circuitry applications, it is highly desirable to form conductive lines having standard or uniform conductive line widths, at least within a region of interest. Conductive line widths which vary between conductive lines can modify the conductive characteristics of the lines, and result in undesirable circuit performance. This problem can be of particular significance in the context of memory circuitry such as dynamic random access memory (DRAM) or static random access memory (SRAM) circuitry.
FIGS. 1 and 2
illustrate a typical processing scenario in which conductive lines having variable widths (and hence variable channel lengths) can be undesirably formed. Referring first to
FIG. 1
, a semiconductor wafer fragment
10
includes a semiconductive substrate
12
. A conductive material layer
14
is formed over substrate
12
and an insulative material layer
16
is formed thereover. Conductive material layer
14
can comprise one or more conductive layers such as conductively doped polysilicon and/or a silicide, and insulative material layer
16
can comprise any suitable insulative material such as various nitrides and/or oxides.
A patterned masking layer
18
is formed over substrate
12
and defines a plurality of conductive lines which are to be subsequently etched from layers
14
,
16
. Each individual masking layer component has a generally uniform or constant length L which will be utilized to define, at least in part, the channel length/gate width of the subsequently etched conductive lines. In theory, the subsequent etching of the conductive lines from the patterned substrate of
FIG. 1
should result in a series of conductive lines having a constant width or channel length. Such has not, however, been observed to occur with dry etching as L fell to and below 0.5 micron, as will become apparent from FIG.
2
.
There, four conductive lines
20
,
22
,
24
, and
26
have been etched from layers
14
,
16
. Yet, the conductive lines have variable widths and hence variable channel lengths in spite of having masking blocks
18
of the same dimension. Conductive lines
20
and
24
constitute “edge lines” which have no immediate conductive line neighbor on only one side thereof. Conductive line
22
comprises a “center line” which has immediate conductive line neighbors on each side thereof. Conductive line
26
comprises an “isolated line” which has no immediate conductive line neighbor on either side thereof.
Edge lines
20
,
24
have widths which vary from center line
22
by a factor
6
, thereby giving an effective channel length of L+&dgr;. Isolated line
26
has a width, and hence a channel length, equal to around L+2&dgr;. Conductive lines having immediately adjacent neighboring lines within a desired or selected distance, i.e. line
22
, on each side thereof have generally uniform or standard widths and channel lengths. On the other hand, conductive lines which do not have immediately adjacent neighboring lines within a desired or selected distance on each side do not have standardized widths or channel lengths, i.e. lines
20
,
24
, and
26
. Accordingly, it would be desirable to eliminate the variability of conductive line widths and hence channel lengths as described above.
This invention arose out of concerns associated with providing improved semiconductor design methods and processing methods directed to providing improved uniformity between conductive line widths and channel lengths.
SUMMARY OF THE INVENTION
Semiconductor circuit design methods, semiconductor processing methods, and related integrated circuitry are described. In one embodiment, a spacing constraint is defined and describes a desired spacing between a transistor gate line and a next adjacent structure. A circuit layout is defined to include a plurality of transistor gate lines. From the circuit layout, at least one area is determined wherein the spacing constraint is not met. The circuit layout is modified by defining in the one determined area, at least one added space-compensating structure which is laterally spaced from a gate line and a next adjacent structure where the spacing constraint is not met.
In another embodiment, a plurality of gate lines are defined which are to be formed over substrate active areas. A determination is made whether a gate line spacing constraint is met wherein the gate line spacing constraint describes a desired spacing between a transistor gate line and a next adjacent transistor gate line. If the spacing constraint is not met, then a space-compensating transistor gate line is added and positioned to satisfy the spacing constraint.
In yet another embodiment, a circuit layout having a memory area defining memory circuitry and a peripheral area defining peripheral circuitry is examined. From the circuit layout is ascertained areas in which retrofit structure patterns are to be added. The circuit layout is retrofitted within the peripheral area with retrofit structure patterns which ensure that desired spacing constraints are met with respect to at least some of the peripheral circuitry when the peripheral circuitry is subsequently patterned and etched.
In yet another embodiment, a semiconductor processing method includes forming a masking layer over a substrate defining a plurality of conductive lines which are to be etched. Some of the defined conductive lines constitute active gate lines positioned over substrate active areas, and other of the defined conductive lines constitute space-compensating conductive lines at least some of which having portions positioned over isolation oxide areas. Some of such other conductive lines are defined by the masking layer only to satisfy a spacing constraint which describes a desired active gate line-to-gate line spacing. Subsequently, the conductive lines are etched through the masking layer.
In yet another embodiment, a semiconductor processing method comprises forming a plurality of conductive lines over a substrate, some of the conductive lines providing transistor gate lines over substrate active areas, other of the conductive lines being formed only to satisfy a spacing constraint which describes a desired spacing between transistor gate lines.
REFERENCES:
patent: 4783749 (1988-11-01), Duzy et al.
patent: 4847672 (1989-07-01), Polhemus
patent: 5051917 (1991-09-01), Gould et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5677241 (1997-10-01), Manning
patent: 5691565 (1997-11-01), Manning
patent: 5757691 (1998-05-01), Hatakeyama
patent: 5856703 (1999-01-01), Manning
patent: 5901065 (1999-05-01), Guruswamy et al.
patent: 5932490 (1999-08-01), Manning
patent: 5953518 (1999-09-01), Sugasawara et al.
patent: 5981397 (1999-11-01), Manning
Micro)n Technology, Inc.
Smith Matthew
Thompson A. M.
Wells St. John Roberts Gregory & Matkin
LandOfFree
Semiconductor circuit design method for employing spacing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor circuit design method for employing spacing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor circuit design method for employing spacing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2454919