Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-02-16
2001-09-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S040000
Reexamination Certificate
active
06292019
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to programmable logic devices, and in particular to a configurable logic block with improved programming flexibility.
BACKGROUND
Programmable logic devices (PLDS) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a logic designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they require less time to implement than semi-custom and custom integrated circuits.
FIG. 1
is a block diagram of one type of PLD, a field-programmable gate array (FPGA)
10
. FPGA
10
includes an array of configurable logic blocks (CLBs)
20
that are programmably interconnected to each other and to programmable input/output blocks (IOBs)
30
. The interconnections are provided by configurable horizontal and vertical interconnect lines
40
and
50
, which may be connected to one another using programmable interconnect points (PIPs). This collection of configurable elements may be customized by loading configuration data into internal configuration memory cells (not shown) that define how the CLBs, PIPs, and IOBs are configured. The configuration data may be read from memory (e.g., an external PROM) or written into FPGA
10
from an external device. The collective states of the individual memory cells then determine the function of FPGA
10
.
Logic designers commonly use multiplexers, or “MUXs,” to dynamically select from among a number of signal sources. Consequently, conventional FPGAs provide dynamic multiplexing functions. In this context, “dynamic” means that the MUXs can be controlled during operation. This is in contrast to many other MUXs in conventional FPGAs that are statically controlled by configuration memory cells.
One type of FPGA allows logic designers to define dynamically controlled MUXs using look-up-table (LUT) based function generators. Such implementations are inefficient, however, because MUXs are simple, input-intensive devices, whereas LUT-based function generators are better suited for performing complex logic functions of a few inputs. For more information regarding conventional FPGAs that include configurable LUT-based function generators, see “The Programmable Logic Data Book,” (1998) pp. 4-5 to 4-40, available from Xilinx, Inc., of San Jose, Calif., which is incorporated herein by reference.
FIG. 2A
schematically depicts a conventional CLB
20
and eight associated input terminals
110
A-H. CLB
20
includes a pair of LUT-based function generators
120
and
130
, each of which connects to four of input terminals
110
A-H. Each of input terminals
110
A-H is programmably connectable to any of sixteen vertical interconnect lines, e.g.,
140
A and
140
P. For example, input terminal
110
A can be programmed to connect with vertical interconnect line
140
A by programming a PIP
145
. The PIPS, the input terminals, and the vertical interconnect lines collectively form a sixteen-input MUX for routing desired signals to function-generators
120
and
130
. The terms “horizontal” and “vertical” are illustrative and not limiting.
Function generators
120
and
130
, with outputs labeled F and G, are each capable of implementing any arbitrarily defined Boolean function of up to four inputs. A third LUT-based function generator
135
can implement any Boolean function of up to three inputs.
CLB
20
includes four statically controlled MUXs
146
A-D that map four dynamic control inputs C
1
-C
4
from outside CLB
20
into four internal control signals H
1
, H
2
, H
0
, and EC. Any of control inputs C
1
-C
4
can drive any of the four internal control signals. Two additional statically controlled MUXs
148
A and
148
B select between function-generator outputs F and G and internal control signals H
1
and H
2
for input to function generator
135
. The signal H
0
on a third input of function generator
135
comes from a signal source external to CLB
20
.
The MUXs and function generators of CLB
20
are some of the components included in a conventional CLB of the type found in the XC4000 family of FPGAs available from Xilinx, Inc. The remaining components of CLB
20
are lumped together in
FIG. 2A
as circuit
150
for ease of illustration. The operational details of CLB
20
are well understood and are therefore omitted for brevity.
FIG. 2B
is a schematic diagram that includes CLE
20
of
FIG. 2A
connected to a two-level, sixteen-input MUX
160
. MUX
160
schematically represents the functionality of input terminal
110
A and associated PIPs and vertical interconnect lines.
MUX
160
includes five four-input MUXs
160
A-E, each of which is controlled by a pair of programmable memory cells (not shown).
FIG. 2B
only depicts a single MUX
160
to function generator
120
for ease of illustration; it is to be understood, however, that similar MUXs are provided for each input terminal
110
A-H of function generators
120
and
130
.
Each of function generators
120
and
130
can implement a two-input MUX. In such a configuration, function generator
120
, for example, is programmed to include a select input and a pair of MUX input terminals. The select and MUX input terminals are chosen from among input terminals
110
A-D such that the logic level on the input terminal representing the select input selects between the signals present two other ones of input terminals
110
A-D. Function generator
135
is also capable of implementing a two-input MUX that can select from F and G outputs of function generators
120
and
130
.
CLB
20
can implement a two-level, four-input MUX by programming each of function generators
120
,
130
, and
135
to implement two-input MUXs. Unfortunately, implementing such a simple function in LUT-based function generators leaves many gates unused, gates that might otherwise be used to perform other functions. This is an inefficient use of CLB
20
. There is therefore a need for a programmable logic device in which the CLBs are equally capable of implementing complex logic functions of few inputs and simple logic functions of many inputs.
SUMMARY
The present invention is directed to a programmable logic device (PLD) that can efficiently implement both complex logic functions of few inputs and simple logic functions of many inputs. As with conventional devices, the inventive PLD includes at least one function generator capable of implementing any arbitrarily defined Boolean function of signals presented on a plurality of function-generator input terminals. Unlike conventional devices, however, the inventive PLD includes a dynamically controlled MUX on each function-generator input terminal. Signals on the input terminals of each MUX can be routed to the corresponding function-generator input terminal by providing an appropriate select signal on one or more control lines. The combination of the function generator and dynamically controlled MUXs provides the same functionality as conventional logic devices while improving the efficiency with which the inventive PLD implements multiplexing functions that require a large number of inputs.
The dynamic MUX configuration can reduce the available routing resources for each function-generator input terminal. To mitigate this, one embodiment includes a programmable look-up table, or “LUT,” that permits routing software to determine the correspondence between the MUX input terminals and a user-defined selection code on the MUX control lines. In one embodiment, the correspondence between the MUX input terminals and the selection code is established by configuring a number of programmable memory cells in the LUT. In another embodiment, the programming flexibility is further enhanced by an additional MUX connected between the control lines and the LUT. This control MUX allows a user to determine which control lines will provide select signals to the first MUX.
REFERENCES:
patent: 5386156 (1995-01-01), Britton et al.
patent: 5905385 (1999-05-01), Sharpe-Geisler
patent: 6020756 (2000-02-01), New
patent: 6118298 (2000-09-01), Bauer et al.
patent: 6191610 (2001-02-01), Wittig
Carberry Richard A.
New Bernard J.
Behiel Arthur J.
Cartier Lois D.
Le Don Phu
Tokar Michael
Xilinx , Inc.
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