Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-04-12
2001-08-14
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S533000, C438S301000, C438S592000, C438S662000, C438S657000
Reexamination Certificate
active
06274488
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a method of forming a silicide region on a silicon substrate in the manufacturing of semiconductor integrated devices, and such devices having a suicide region formed by the method of the present invention.
BACKGROUND OF THE INVENTION
Improvements in semiconductor technology and semiconductor manufacturing are the main drivers to the reduction of cost and the increase in speed of computers. There have been many advances for increasing the speed of semiconductor devices, ranging from packaging of integrated circuits (“chips”) to the wiring of the devices on the chip, to the devices themselves.
Improvements in chip manufacturing techniques include new processes (or improving an existing process) for making the chip. Such improvements may include new, faster and more efficient ways of creating the necessary device structures. For example, many techniques have been developed for forming silicide regions for integrated device contacts, particularly for metal-oxide-semiconductor (MOS) devices formed on silicon substrates. Most of these techniques involve the formation of a metal layer over a gate, drain or source region upon which the silicide is desired to be formed. These techniques then use a thermal treatment to react the metal with the silicon composing the gate, drain and/or source regions, to form the low-resistivity silicide regions. The substrate is further processed by removing the unreacted metal layer, then forming an electrically-insulating layer over the substrate, and finally forming conductive metal lines on the insulating layer. These metal lines can contact the silicide regions over the gate, source and drain regions to form the desired circuit connections for an integrated MOS device.
Techniques for forming suicides are subject to several stringent process constraints that must be met in order for such techniques to be effective. These constraints include: (1) the metal used to form the silicide must be carefully selected to be a species that diffuses into the silicon, to avoid the formation of leakage paths between the source, drain and gate of an integrated device; (2) for self-aligned silicidation techniques, the metal layer must not react with the insulative material composing the self-aligning side walls of the gate; (3) the dopants must not segregate into the silicide regions, which makes it difficult to achieve low contact resistance; (4) the technique should have a process window that allows the silicide region to be formed on both crystalline-silicon and poly-silicon; (5) the silicide formation should be insensitive to dopants present in the silicon; and (6) the metal atoms should not diffuse beyond the suicide regions, that is, into the silicon. If metal atoms diffuse into the silicon, junction leakage will likely increase. The simultaneous fulfillment of all of the above-stated criteria is at best difficult for most conventional silicidation techniques, especially those that use relatively extensive thermal treatments. Most often, a failure to perform the conventional technique within its relatively narrow process margins manifests itself as defects due to thermal drift of the metal atoms beyond desired boundaries during the relatively prolonged thermal treatment periods. If the silicide region extends beyond its design dimensions, it can result in-leakage paths between the gate and the source and drain. Therefore a great need exists for a technique that enhances silicidation process margins beyond those conventionally available.
U.S. Pat. No. 5,888,888 (the '888 patent) discloses a method of producing a silicide region on a Si substrate. The '888 patent is incorporated herein by reference. The method disclosed in the '888 patent is useful for a variety of purposes, including the reduction of the electrical contact resistance to the Si substrate or an integrated electronic device formed thereon. The method includes the step of irradiating a metal layer formed atop the source and drain regions with front side irradiation i.e., irradiating the metal layer from the front side of the silicon substrate to initiate diffusion of the metal into the silicon substrate. While this method is very useful, it would still be preferable to be able to heat the metal layer by other means that result in quicker silicidation.
SUMMARY OF THE INVENTION
The present invention pertains to a method of forming a silicide region on a silicon substrate in the manufacturing of semiconductor integrated devices, and such devices having a silicide region formed by the method of the present invention.
Accordingly, a first aspect of the invention is a method of forming a silicide region in a crystalline Si substrate having an upper surface and a lower surface. The method comprises the steps of first, forming an amorphous doped region in the Si substrate at or near the upper surface to a predetermined depth. This results in an interface being formed between the amorphous doped region and the crystalline Si substrate. This interface is referred to herein as the amorphous-crystalline interface. The next step is forming a metal layer on the upper surface of the Si substrate, in contact with the amorphous doped region. The next step is then performing backside irradiation with a first radiation beam to heat the interface to initiate explosive recrystallization (XRC) of the region. This provides heat to the metal layer sufficient to cause diffusion of metal from the metal layer into the amorphous doped region, as described in greater detail below. The diffusion of the metal, in turn, results in the silicide region being formed in the amorphous doped region at or near the upper surface of the Si substrate.
A second aspect of the invention is a method of forming a MISFET device in a Si substrate having upper and lower surfaces and silicide regions. The method comprises the steps of first, forming spaced apart shallow trench isolations in the Si substrate. The next step is forming, atop the upper surface of the Si substrate and between the shallow isolation trenches, a gate having sides. The next step is then performing a first amorphization and doping of first and second portions of the Si substrate adjacent the gate to form extension regions having a first predetermined depth from the upper surface. The next step is forming sidewall spacers adjacent the sides of the gate. The next step is then performing a second amorphization and doping of the substrate adjacent the sidewall spacers to transform portions beneath the extensions to deep drain and deep source regions having a second predetermined depth from the upper surface, and first and second amorphous-crystalline interfaces within the Si substrate. At this point, the deep drain and the extension above it can be considered a single “drain” region. Likewise, the deep source and the extension above it can be considered a single “source” region. The next step is depositing a metal layer atop the upper surface of the Si substrate over the drain and source regions. The next step is performing backside irradiation. This is accomplished using a first radiation beam incident the lower surface of the Si substrate. The energy from this beam is used to initiate XRC at the first and second amorphous-crystalline interfaces such that heat is provided to the deep drain and source regions and propagates toward the upper surface of the Si substrate and the metal layer so as to initiate diffusion of metal in the metal layer into upper portions of the drain and source regions. This results in the formation of the silicide regions in the upper portions of the drain and source regions. The silicide regions so formed have a low sheet resistance, i.e., 5&OHgr;/sq or less. The final step is removing the metal layer that remains after the diffusion of metal is completed.
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patent: 4622735 (1986-11-01), Shibata
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patent: 4830971 (1989-05-01), Shibata
patent: 4924294 (1990-05-01), Tanielian
patent: 49
Talwar Somit
Wang Yun
Bowers Charles
Jones Allston L.
Nguyen Thanh
Ultratech Stepper, Inc.
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