Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1997-07-25
2001-06-05
Bragdon, Reginald G. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S152000
Reexamination Certificate
active
06243793
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to communication between computer systems. More specifically, the present invention relates to an apparatus and method for arbitrating access to a shared memory area.
BACKGROUND OF THE INVENTION
When processors share a common memory area, coordination of memory access between the processors is necessary. Coordination of memory access insures that data written in the shared memory area are not prematurely overwritten by one processor before being read by another processor. Coordination of memory access also insures that two processors will not simultaneously attempt to access the shared memory area. Without coordination of memory access, systems sharing a common memory area may experience data loss or more seriously, hardware failure.
One approach to coordinating memory access is the use of a master processor. A master processor manages the activities of slave processors on shared memory. A master processor keeps track of the different areas in memory which are accessed and the purpose for which they are used. Each slave processor seeking access to the shared memory must first receive permission from the master processor. Typically, the master processor arbitrates memory access between slave processors by taking into account the priority of the tasks to be performed and whether the memory is currently being accessed by another processor.
Another approach for coordinating memory access is self-arbitration of processors through the use of an out-of-band transmission path. Typically, a separate bus which is not a memory-access bus is used to transmit state information from one processor to another sharing the common memory area. This allows the processors to coordinate memory access among themselves. For example, after a first processor is finished writing data to a location in the shared memory, the first processor can give access to that location of shared memory to a second processor to read that information by signaling the second processor through the out-of-band transmission path. Only the second processor can access the shared memory at that time for that specific purpose.
The use of a master processor has several drawbacks. Typically, processors require a large amount of power to operate. This is a problem for computer systems operating under tight power constraints, such as systems operating with batteries. Processors are also relatively large in size compared to other IC components. Thus, depending upon the environment of the computer system, the availability of physical space may not permit the implementation of an additional processor. Perhaps most importantly, the use of an additional processor for the purpose of memory arbitration adds an undesirable cost to the overall computer system.
Self-arbitration also has its limitations. Computer systems wishing to implement self-arbitration must provide an out-of-band transmission path to allow the processors sharing the memory space to communicate with each other. Design specifications of some computer systems may not permit the implementation of an out-of-band transmission path.
Thus, a method and apparatus for arbitrating access to a shared memory which does not require the implementation of an additional processor or an out-of-band transmission path is needed.
SUMMARY OF THE INVENTION
An apparatus and method for arbitrating access to a shared memory is disclosed. One embodiment of a memory unit of the present invention comprises a memory cell for storing data. An access indication unit is coupled to the memory cell. The access indication unit indicates the identity of a first processor accessing the memory cell. A state recorder unit is coupled to the access indication unit. The state recorder unit records a task performed by the first processor. A semaphore unit is also coupled to the access indication unit. The semaphore unit reads the access indication unit and prevents a second processor from accessing the memory cell while the first processor is accessing the memory cell. An arbitration unit is coupled to the access indication unit. The arbitration unit operates to restrict access of the memory cell to one processor at a time.
One embodiment of a system for providing communication between a first computer system and a second computer system of the present invention comprises a memory connecting the first computer system to the second computer system. The memory stores data transferred between the first computer system and the second computer system. An access indication unit is coupled to the memory. The access indication unit indicates the identity of a computer system having access to the memory. A state recorder unit is coupled to the access indication unit. The state recorder unit records a task performed by the processor as a state. A first state engine is coupled to the state recorder unit. The first state engine instructs the first processor how to process the data in the memory in response to reading a previous task recorded in the state recording unit. A second state engine is coupled to the state recorder unit. The second state engine instructs the second processor how to process the data in the memory in response to reading the previous task recorded in the state recording unit.
One embodiment of a method for sending data between a first processor and a second processor comprises the steps of first checking a shared memory space for availability. After checking the shared memory space, identifying a last task performed on the shared memory space. From the last task, determining whether a current task with higher priority must be performed first. Next, transmitting data between the first processor and the shared memory space. After the data are transmitted, recording the present task performed on the shared memory space.
REFERENCES:
patent: 4402046 (1983-08-01), Cox et al.
patent: 5274809 (1993-12-01), Iwasaki et al.
patent: 5377352 (1994-12-01), Tanaka et al.
patent: 5455920 (1995-10-01), Muramatsu
patent: 5485593 (1996-01-01), Baker
patent: 5754800 (1998-05-01), Lentz et al.
Aucsmith David W.
Knauerhase Robert C.
Stanley James C.
Blakely , Sokoloff, Taylor & Zafman LLP
Bragdon Reginald G.
Intel Corporation
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