Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-28
2001-01-09
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257S346000
Reexamination Certificate
active
06172395
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to methods of manufacture of semiconductor memory devices and the devices manufactured thereby and more particularly to flash memory devices and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,612,249 of Sun et al. for “Post-Gate LOCOS” shows a process comprising: etching a gate oxide layer and a polysilicon layer to form gate structures for the FETs; surrounding the gate structures with an oxidation mask; etching areas of the top surface of the substrate which do not include the gate structures of the FETs such that the substrate is thicker underneath the gate structures for the FETs than it is at other areas of the substrate; and forming the LOCOS field oxide isolation regions by growing an oxide layer between the FETs. Sun patent '249 shows the concept of using isolation to self-align the S/D regions; but has the disadvantage that a complicated process is described requiring a series of steps to pattern the gates and form the trenches.
Aritome et al. for “A 0.67 &mgr;m
2
Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) for 3 V-only 256 Mbit NAND EEPROMS” IEDM 94-61 Pages 3.6.1-3.6.4 describes a floating gate that is “self-aligned with the STI.”
U.S. Pat. No. 5,120,671 of Tang for a “Process for Self Aligning a Source with a Field Oxide Region and a Polysilicon Gate” and U.S. Pat. No. 5,376,573 of Richart et al. for a “Method of Making a Flash EPROM Device Utilizing a Single Masking Step for Etching and Implanting Source Regions within the EPROM Core and Redundancy Areas” shows a method for forming contact trenches and isolation trenches. The above Tang and Richart et al. references are based on LOCOS for isolation.
U.S. Pat. No. 5,217,920 of Mattox et al. shows a “Method of Forming Substrate Contact Trenches and Isolation Trenches Utilizing Anodization for Isolation” discloses features which differ from the present invention in that it provides for a buried contact.
FIGS.
1
A-
1
G show processing steps for a prior art method for manufacturing a self-aligned floating gate flash memory cell. Some problems with the process are as follows:
1. Two separate photolithography masks are required to define active area and floating gate electrode, respectively.
2. Misalignment between these two photolithography masks limits the shrink scale for a Flash memory cell.
3. The LOCOS method limits the shrinkage of the width of the active area for Flash memory cells.
The process with the device
8
as seen in
FIG. 1A
begins with silicon substrate
10
with a pad silicon oxide layer
11
formed thereon. Above pad oxide layer
11
are formed silicon nitride masking strips
12
A,
12
B, which are employed during formation of the active region of the device employing the well known LOCOS (LOCal Oxidation of Silicon) process.
In
FIG. 1B
, the device of
FIG. 1A
is shown after a silicon nitride masking strips
12
A and
12
B are then stripped from the device
8
leaving a structure comprising a series of parallel FOX (Field OXide) region strips
16
A,
16
B and
16
C formed on substrate
10
.
As shown in
FIG. 1C
a tunnel oxide layer
17
has been formed on the exposed surface of the substrate
10
of
FIG. 1B
, aside from the FOX region strips
16
A,
16
B and
16
C. A blanket doped polysilicon layer
18
is formed on device
8
.
FIG. 1D
shows the device of
FIG. 1C
after a floating gate mask has been formed to pattern the layer
18
into floating gate electrodes
18
A and
18
B bridging between FOX region strips
16
A and
16
B on the left and between and FOX region strips
16
B and
16
C on the right. There is the potential of misalignment with the two masking steps required to achieve the results shown in
FIGS. 1B and 1D
.
In
FIG. 1E
the device of
FIG. 1D
is shown after an interpolysilicon dielectric, ONO, layer
20
is grown. Then as shown a second polysilicon layer
22
is formed over the ONO layer
120
and a tungsten silicide layer
24
formed over the second polysilicon layer
22
. Layer
22
and layer
24
are to be patterned into control gate electrodes stacks
22
/
24
on a step-by-step basis.
FIG. 1F
shows the device of
FIG. 1E
after a Stacked Gate Etch (SGE) mask (not shown) has been used to etch away exposed portions of layers on the periphery of device
8
after the silicide layer
24
, polysilicon
22
, ONO layer
20
and first polysilicon layer
18
A,
18
B through that mask yielding the structure seen in
FIG. 1F
with the surface of the FOX regions
16
A,
16
B and
16
C exposed beyond the remaining gate electrode stack
28
.
FIG. 1G
shows the device of
FIG. 1F
after the self-aligning source mask has been used to etch away the exposed portions of the FOX regions
16
A,
16
B and
16
C to expose the surfaces of the substrate to form S (source) regions
30
A and
30
B adjacent to the floating gates
18
A and
18
B. The drain regions (not seen) are formed on the opposite side of the gate electrode stack
28
from the source regions
30
A and
30
B.
SUMMARY OF THE INVENTION
Problems solved and the improvements obtained by this invention include as follows:
1. Only a single masking layer is required instead of two conventional layers to define an active area and a floating gate electrode.
2. The problems associated with a misalignment between the two masks usually employed for defining the active area and the floating gate electrode is completely avoided and the space between the active areas of two adjacent cell can be scaled down, easily.
3. Because of the planarization of device topography, the following etch steps, for example: stacked gate electrode etch and contact hole etch, become much easier.
4. Application of trenched source line implant can save the space between stacked gate electrode.
In accordance with this invention, a method of manufacture of self-aligned floating gate, flash memory device on a semiconductor substrate comprises the steps which follow.
Make a threshold voltage adjustment implant. Form a blanket tunnel oxide layer over the substrate. Form a blanket floating gate doped polysilicon layer over the silicon oxide layer. Patterning the blanket silicon oxide layer, the floating gate, polysilicon layer and the substrate in a patterning process with a single mask forming a floating gate electrode from the floating gate polysilicon layer and the tunnel oxide layer and simultaneously forming trenches in the substrate adjacent to the floating gate electrode and aligned therewith. Form a trench dielectric structure on the surface of the device by the following steps. Form a blanket, thin thermal oxide dielectric layer on the device including the trenches and covering the floating gate conductor layer. Form a blanket, thin PECVD silicon oxide dielectric layer on the device including the trenches and covering the thin thermal oxide dielectric layer. Then form a blanket, SACVD silicon oxide dielectric layer on the device filling the trenches and covering the device with a thick film of silicon oxide material. Planarize the trench dielectric structure with the surface of the floating gate conductor by a CMP processing step. Form an interconductor ONO dielectric layer over the device. Form a control gate conductor over the interconductor dielectric layer.
Preferably, the blanket silicon oxide layer comprises a tunnel oxide layer with a thickness from about 70 Å to about 150 Å; and the floating gate conductor layer comprises a doped polysilicon layer having a thickness from about 500 Å to about 2,000 Å.
Preferably, the blanket trench dielectric structure on the device comprises first a thin, thermal, silicon oxide layer with a thickness from about 200 Å to about 500 Å grown by a conventional thermal oxidation process on the exposed surfaces at the bases of trench structures. Second a PECVD silicon oxide layer having a thickness from about 200 Å to about 2,000 Å is coated on the surfaces of the thermal silicon oxide layer, and third a SACVD silicon oxide layer having a thickness from ab
Chen Jong
Jung Lin Chrong
Ackerman Stephen B.
Goodwin David S
Jones II Graham S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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