Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-25
2001-05-15
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S343000, C257S655000
Reexamination Certificate
active
06232636
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is in the field of Semiconductor-On-Insulator (SOI) devices, and relates more particularly to lateral SOI devices suitable for high-voltage applications.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, “on” resistance and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as “on” resistance. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
One particularly advantageous form of lateral thin-film SOI device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOS device on the buried insulating layer, the MOS device, such as a MOSFET, including a semiconductor surface layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first, an insulated gate electrode over a channel region of the body region and insulated therefrom by an insulation region, a lateral drift region of the first conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region.
A device of this type is shown in
FIG. 1
common to related U.S. Pat. Nos. 5,246,870 (directed to a method) and 5,412,241 (directed to a device), commonly-assigned with the instant application and incorporated herein by reference. The device shown in
FIG. 1
of the aforementioned patents is a lateral SO MOSFET device having various features, such as a thinned SOI layer with a linear lateral doping profile in the drift region and an overlying field plate, to enhance operation. As is conventional, this device is an n-channel or NMOS transistor, with n-type source and drain regions, manufactured using a process conventionally referred to as NMOS technology.
More advanced techniques for enhancing high-voltage and high-current performance parameters of SO power devices are shown in U.S. patent application Ser. No. 08/998,048, filed Dec. 24, 1997, commonly-assigned with the instant application and incorporated herein by reference. Yet another technique for improving the performance of an SOI device is to form a hybrid device, which combines more than one type of device configuration into a single structure. Thus, for example, in U.S. patent application Ser. No. 09/122,407, filed Jul. 24, 1998, commonly-assigned with the instant application and incorporated herein by reference, an SOI device is disclosed which includes a lateral DMOS transistor and an LIGB transistor in the same structure.
Thus, it will be apparent that numerous techniques and approaches have been used in order to enhance the performance of power semiconductor devices, in an ongoing effort to attain a more nearly optimum combination of such parameters as breakdown voltage, size, current-carrying capability and manufacturing ease. While all of the foregoing structures provide varying levels of improvement in device performance, no one device or structure fully optimizes all of the design requirements for high-voltage, high-current operation.
Accordingly, it would be desirable to have a transistor device structure capable of high performance in a high-voltage, high-current environment, in which operating parameters, and in particular “on” resistance and breakdown voltage, are further optimized.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a transistor device structure capable of high-performance in a high-voltage, high-current environment. It is a further object of the invention to provide such a transistor device structure in which operating parameters such as “on” resistance and breakdown voltage are enhanced.
In accordance with the invention, these objects are achieved in a lateral thin-film SOI device structure of the type described above in which the lateral drift region has a graded lateral doping profile, with a first portion of the lateral drift region adjacent the body region having a first substantially linearly graded lateral doping profile having a first doping profile slope, and a second portion of the lateral drift region adjacent the drain region having a second substantially linearly graded lateral doping profile having a second doping profile slope which is greater than that of the first doping profile slope.
In a preferred embodiment of the invention, the insulation region has a discontinuity in thickness at a point above the drift region and adjacent the body region, and a transition from the first doping profile slope to the second doping profile slope in the lateral drift region occurs in a region of the drift region approximately beneath the discontinuity in the insulation region.
In a further preferred embodiment of the invention, the second doping profile slope is in the range of about 1.3 to 1.4 times greater than the first doping profile slope.
Lateral thin-film SOI devices in accordance with the present invention offer a significant improvement in that a combination of favorable performance characteristics making the devices suitable for operation in a high-voltage, high-current environment, such as low “on” resistance and high breakdown voltage, can be achieved.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 5246870 (1993-09-01), Merchant
patent: 5300448 (1994-04-01), Merchant et al.
patent: 5378912 (1995-01-01), Pein
patent: 5412241 (1995-05-01), Merchant
patent: 5438220 (1995-08-01), Nakagawa et al.
patent: 5578506 (1996-11-01), Lin
patent: 5648671 (1997-07-01), Merchant
patent: 5710451 (1998-01-01), Merchant
patent: 5767547 (1998-06-01), Merchant et al.
patent: 5780900 (1998-07-01), Suzuki et al.
Letavic Theodore
Simpson Mark
Biren Steven R.
Philips Electronics North America Corporation
Prenty Mark V.
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