Method of fabricating copper damascene

Details Method of fabricating copper damascene Method of fabricating copper damascene

1999-06-18

2001-05-22

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S619000, C438S622000, C438S687000

Reexamination Certificate

active

06235625

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88106719, filed Apr. 27, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a multi-level interconnect of a semiconductor feature. More particularly, the invention relates to a method of fabricating a copper (Cu) damascene and a Cu dual damascene.
2. Description of Related Art
It was known that the semiconductor manufacture has entered the deep sub-micron process. In addition to a reduction of the transistor size to increase the device operation speed in such process, the operation speed and reliability of the device can be further increased by manufacturing the device with different materials.
In the backend process of the semiconductor device, the current RC time delay in a metal line has gradually increased as the width of the metal line is reduced. This may easily produce an electron migration (EM) effect in the conventional metal line formed mainly of aluminum (Al), therefore reducing the reliability of the device.
To resolve the above problems encountered by the semiconductor device in the deep sub-micron process, copper (Cu) with a lower resistance and minimum EM effect is adopted and has thus become the uniform choice for all semiconductor device manufacturers.
However, as Cu is not easily etched with common etching gases, a Cu metal line would not be manufactured by a conventional method. A Cu damascene process is therefore proposed.
FIGS. 1A
to
1
F are schematic diagrams showing the process flow for fabricating a conventional Cu dual damascene.
Referring to
FIG. 1A
, a silicon oxide (SiO
x
) layer
102
is formed to cover a substrate
100
. A silicon nitride (SiN
x
) layer
104
is then formed to cover the SiO
x
layer
102
, while a SiO
x
layer
106
is further formed to cover this SiN
x
layer
104
.
The SiO
x
layer
102
, the SiN
x
layer
104
, and the SiO
x
layer
106
are made into an inter-metal dielectric layer (IMD layer) in which the method may involve a plasma enhanced chemical vapor deposition (PECVD).
Referring to
FIG. 1B
, a trench line
108
is formed in the SiO
x
layer
106
by photolithography and etching. In the defining process for the trench line
108
, the SiN
x
layer
104
is used as an etching stop layer to prevent the over etching during the formation of the trench line
108
.
Referring to
FIG. 1C
, the SiN
x
layer
104
and the SiO
x
layer
102
located at a bottom of the trench line
108
are defined by further photolithography and etching, so that a via
110
is formed at the bottom of the trench line
108
.
Referring to
FIG. 1D
, a barrier layer
112
and a Cu layer
114
are formed in sequence to cover the trench line
108
, the via
110
, and the SiO
x
layer
106
. The barrier layer
112
and the Cu layer
114
may be formed by physical vapor deposition (PVD) or CVD.
Referring to
FIG. 1E
, a Cu electroplating is performed, with the Cu layer
114
serving as a seeding layer, to form a Cu layer
116
that covers the Cu layer
114
.
Referring to
FIG. 1F
, the barrier layer
112
and the Cu layers
114
,
116
, which layers cover a top surface of the SiO
x
layer
106
are removed, so that only a barrier layer
112
a
and Cu layers
114
a
,
116
a
remain in the trench line
108
and the via
110
.
The method for removing the barrier layer
112
and the Cu layers
114
,
116
that cover the top surface of the SiO
x
layer
106
may involve chemical mechanical polishing (CMP).
With the continuing shrinkage of the device size, it is not easy to maintain an excellent conformity of a Cu seeding layer in a structure with a high aspect ratio by PVD.
Furthermore, the Cu seeding layer formed by CVD has a poor quality for its film, while the cost for manufacturing the Cu layer by CVD is very high.
As it is necessary to form the Cu seeding layer by PVD or CVD using additional machines, the cost to perform the conventional fabricating method is higher.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating a Cu damascene. The Cu seeding layer maintains an excellent conformity and film quality in a structure with a high aspect ratio.
The invention provides a method of fabricating the Cu damascene, the method comprises steps of providing a substrate, forming a dielectric layer to cover the substrate, and forming a trench line and a via in the dielectric layer, wherein the via is below the trench line. The method further comprises steps of forming a barrier layer to conformally cover the trench line, the via, and the dielectric layer, forming an amorphous silicon layer to cover the barrier layer, and forming a photoresist layer to cover the amorphous silicon layer and to fill the trench line and the via. The photoresist layer and the amorphous silicon layer on atop surface of the barrier layer are then removed, followed by the removal of the photoresist layer in the trench line and the via, so that only the amorphous silicon layer and the barrier layer remain in the trench line and the via. A Cu displacement is performed to displace the amorphous silicon layer with a first Cu layer. The trench line and the via are eventually filled with a second Cu layer, while the barrier layer on the dielectric layer is removed.
According to the present invention, an amorphous silicon layer is formed in the trench line and the via, while a Cu displacement is performed to displace the amorphous silicon layer with a Cu layer. With the Cu layer serving as a seeding layer, a Cu electroplating or a Cu electroless plating is performed to selectively fill the trench line and the via with the Cu layer.
In the invention, the amorphous silicon layer with an excellent conformity is used as a displacing material. Therefore, the Cu seeding layer maintains its excellent conformity and film quality in the structure with a high aspect ratio, even though the device size is gradually reduced.
The time to perform a Cu CMP is reduced because the Cu layer selectively fills the trench line and the via, so the throughput of product is improved.
As the fabricating method disclosed by the invention can be achieved with the currently available machines, there is no need to use new machines, such as PVD or CVD Cu machine, thus reducing the cost of the production.
The Cu displacement disclosed by the invention can be performed together with the Cu electroplating or Cu electroless plating in a same machine, and thus beneficial to the process integration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5693563 (1997-12-01), Teong
patent: 6004188 (1999-12-01), Roy

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