Semiconductor memory device including an SOI substrate

Details Semiconductor memory device including an SOI substrate Semiconductor memory device including an SOI substrate

2000-02-07

2001-09-11

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S230060

Reexamination Certificate

active

06288949

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory (DRAM) formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
A semiconductor memory device is typically divided into a volatile memory such as a RAM, and a non-volatile memory such as a ROM. The volatile memory is further divided into a DRAM and a static random access memory (SRAM). The non-volatile memory includes a mask ROM, an EPROM, a flash memory, an EEPROM, a fuse ROM, and the like.
A DRAM has data stored by accumulating charge in the capacitor of a memory cell. Although such a DRAM requires a refresh operation, a DRAM having a large storage capacity can be manufactured at a low cost due to its simple structure of the memory cell.
Because data is stored by accumulating charge in a capacitor in a DRAM, the amount of charge stored in a capacitor is altered according to &agr; particles emitted from its package or interconnection material. This change in the amount of charge will result in data inversion, i.e., soft error.
The demand for DRAMs having a higher integration density is also great. The potential of mass production is appreciable for DRAMs having a large storage capacity such as 256M bits and 1G bits. Although the gate length is generally reduced to increase the integration density of a DRAM, this reduction in gate length has a limitation due to a significant short channel effect as the channel length is reduced.
In recent years, large scaled integrated circuits (LSI) are developed having circuit elements such as transistors formed on an SOI substrate with an insulation layer buried in the semiconductor substrate.
FIG. 92
is a plan view showing a structure of a MOS transistor formed on an SOI substrate.
FIGS. 93 and 94
are sectional views of the MOS transistor shown in
FIG. 92
taken along lines
93
—
93
and
94
—
94
, respectively.
Referring to
FIGS. 92-94
, an MOS transistor includes an n
+
type source region
1
, an n
+
type drain region
2
, a p type body region
3
, and a gate electrode
4
. Body region
3
is located between source region
1
and drain region
2
. When a predetermined potential is applied to gate electrode
4
, a channel is formed in body region
3
.
This MOS transistor is completely enclosed by a LOCOS oxide film
5
for isolation from an adjacent element. This MOS transistor is formed on an SOI substrate
6
. SOI substrate
6
includes a silicon substrate
7
, a buried oxide film
8
of SiO
2
, and an SOI active layer
9
. Source region
1
, drain region
2
, and body region
3
are formed in this SOI active layer
9
.
Body region
3
attains a floating state electrically since it is enclosed by LOCOS oxide film
5
and isolated from silicon substrate
7
by buried oxide layer
8
. When body region
3
attains a floating state, the breakdown voltage between the source and drain becomes as low as approximately 3V due to a parasitic bipolar operation. There is also a possibility of a leakage current flow between the source and the drain. Furthermore, a body region
3
attaining a floating state induces the generation of a kink to disturb the drain current Id—drain voltage Vd characteristics. Therefore, the transistor cannot operate stably.
SUMMARY OF THE INVENTION
In view of the foregoing, a main object of the present invention is to provide a semiconductor memory device formed on an SOI substrate.
Another object of the present invention is to provide a DRAM with almost no generation of a soft error.
A further object of the present invention is to provide a DRAM having a greater storage capacity.
Still another object of the present invention is to further increase the data retaining time in a memory cell.
A still further object of the present invention is to improve the breakdown voltage between the source and drain of a MOS transistor in a semiconductor memory device.
Yet a further object of the present invention is to reduce leakage current between the source and drain of a MOS transistor in a semiconductor memory device.
Yet another object of the present invention is to operate a MOS transistor stably in a semiconductor memory device.
Yet a still further object of the present invention is to minimize increase in the layout area.
A semiconductor memory device according to an aspect of the present invention includes a plurality of N and P channel MOS semiconductor elements. The plurality of N and P channel MOS semiconductor elements are formed on an SOI substrate. Each MOS semiconductor element includes a source region, a drain region, and a body region located between the source and drain regions. At least one N channel MOS semiconductor element of the plurality of N channel MOS semiconductor elements has its body region electrically fixed. At least one P channel MOS semiconductor element of the plurality of P channel MOS semiconductor elements has its body region rendered floating electrically.
A semiconductor memory device according to another aspect of the present invention includes a plurality of N and P channel MOS semiconductor elements. The plurality of N and P channel MOS semiconductor elements are formed on an SOI substrate. Each MOS semiconductor element includes a source region, a drain region, and a body region located between the source and drain regions. Any body region of the plurality of N channel MOS semiconductor elements is fixed electrically. All the body regions of the plurality of P channel MOS semiconductor elements are rendered floating electrically.
A semiconductor memory device according to a further aspect of the present invention includes a plurality of N and P channel MOS semiconductor elements. The plurality of N and P channel MOS semiconductor elements are formed on an SOI substrate. Each MOS semiconductor element includes a source region, a drain region and a body region located between the source and drain regions. All the body regions of the plurality of N channel MOS semiconductor devices are fixed electrically. All the body regions of the plurality of P channel MOS semiconductor elements are rendered floating.
A semiconductor memory device according to still another aspect of the present invention includes a plurality of MOS capacitors. The plurality of MOS capacitors are formed on an SOI substrate. Each MOS capacitor includes a source region, a drain region connected to the source region, and a body region located between the source and drain regions. At least one MOS capacitor of the plurality of MOS capacitors has its body region connected to its own source region.
A semiconductor memory device according to still a further aspect of the present invention includes a plurality of MOS transistors and a plurality of bit line pairs for storing data. The stored data is read out via a bit line pair. The plurality of MOS transistors and the plurality of bit line pairs are formed on an SOI substrate. Each MOS transistor includes a source region, a drain region, and a body region located therebetween. The body region of a MOS transistor out of the plurality of MOS transistors having a source region or a drain region connected to any of the plurality of bit line pairs is electrically fixed.
A semiconductor memory device according to yet a further aspect of the present invention includes a plurality of MOS transistors. The plurality of MOS transistors are formed on an SOI substrate. Each MOS transistor includes a source region, a drain region, and a body region located therebetween. A variable potential is supplied to the body region of at least one of the plurality of MOS transistors. This variable potential is the reverse voltage with respect to the PN junction between one of the source and drain regions and the body region. Preferably, the body region of the at least one MOS transistor is connected to its own source region.
A semiconductor memory device according to yet another aspect of the present invention includes a plurality of bit line pairs, and a plurality of sense amplifiers. The

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