Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

Reexamination Certificate

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Details

C365S203000, C365S207000, C365S208000

Reexamination Certificate

active

06256246

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a portion thereof concerning differential amplify operation.
2. Description of the Background Art
A semiconductor memory device, particularly a dynamic random access memory (referred to as DRAM hereinafter), is provided with a circuit for differential-amplifying the potential difference between a pair of bit lines generated by charge read out from a memory cell to the bit line pair.
FIG. 15
is a circuit diagram showing a structure of a conventional semiconductor memory device, a DRAM in particular. This semiconductor memory device is formed on a semiconductor substrate
100
. A memory cell
1
is connected to one of a pair of bit lines BL and /BL, for example to bit line BL. Memory cell
1
includes a capacitor
1
C for storing data and an N channel MOS transistor (NMOS transistor)
1
T. NMOS transistor
1
T is connected between capacitor
1
C and bit line BL. The gate thereof is connected to a word line WL.
Between bit line pair BL and /BL, a first sense amplifier SA
1
which is the first differential amplify means, a second sense amplifier SA
2
which is the second differential amplify means, and an equalizer EQ which is the precharge means are connected.
First sense amplifier SA
1
includes NMOS transistors
4
,
5
, and
12
. NMOS transistors
4
and
5
are connected in series between bit line pair BL, /BL. NMOS transistors
4
and
5
have their sources connected to each other, and their drains connected to bit line BL and bit line /BL, respectively. NMOS transistor
4
has its gate connected to bit line /BL, and NMOS transistor has its gate connected to bit line BL. This connection implements cross coupled NMOS transistors
4
and
5
.
NMOS transistor
12
is connected between an outgoing line node Z which is the node between NMOS transistors
4
and
5
and a ground node
11
receiving ground potential GND. The gate of NMOS transistor
12
is applied with a sense operation activating signal SON.
Second sense amplifier SA
2
includes P channel MOS transistors (referred to as PMOS transistor hereinafter)
6
,
7
and
14
. PMOS transistors
6
and
7
are connected in series between bit line pair BL and /BL. PMOS transistors
6
and
7
have their sources connected to each other, and their drains connected to bit line BL and bit line /BL, respectively. PMOS transistors
6
and
7
have their gates connected to bit lines /BL and BL, respectively. Such a connection implements cross coupled PMOS transistor
6
and
7
.
A PMOS transistor
14
is connected between a supply line node Y which is the node between PMOS transistors
6
and
7
and a power supply node
13
receiving power supply potential VCC. The gate of PMOS transistor
14
is applied with a sense operation activating signal SOP.
Equalizer EQ includes NMOS transistors
8
,
9
and
10
. NMOS transistor
8
is connected between the pair of bit lines BL and /BL. NMOS transistor
9
is connected between bit line BL and a potential node Vpr receiving a potential of ½ the power supply potential VCC. NMOS transistor
10
is connected between bit line /BL and potential node vpr. Each gate of NMOS transistors
8
,
9
and
10
is applied with a precharge activating signal BLEQ.
An NMOS transistor
15
is connected between outgoing line node Z and potential node Vpr. An NMOS transistor
16
is connected between supply line node Y and potential node Vpr. Each gate of NMOS transistors
15
and
16
is applied with a precharge activating signal BLEQ.
On bit line pair BL and /BL, NMOS transistors
2
and
3
for connecting first and second sense amplifiers SA
1
and SA
2
and equalizer EQ with memory cell
1
are provided between memory cell
1
, and first and second sense amplifiers SA
1
, SA
2
and equalizer Q. NMOS transistor
2
is provided at bit line BL and NMOS transistor
3
is provided at bit line /BL. NMOS transistors
2
and
3
are activated by activating signal BLI.
The operation of a semiconductor memory device of the above-described structure is described hereinafter. In a standby state (precharge state) of this device, bit line pair BL, /BL, outgoing line node Z, and supply line node Y are precharged to a potential of ½ VCC (referred to as precharge potential hereinafter).
Precharge is effected by precharge activating signal BLEQ attaining a high level to activate NMOS transistors
8
,
9
,
10
,
15
and
16
. More specifically, precharge is carried out by respective short-circuits between bit line pair BL, /BL and potential node Vpr, between outgoing line node Z and potential node Vpr, and between supply line node Y and potential node Vpr.
A data read out operation from memory cell
1
is described hereinafter. In a read out operation, data is transmitted from memory cell
1
to bit line BL, followed by an amplify operation by first and second sense amplifiers.
FIG. 16
is a signal waveform diagram of each component in circuitry at the time of a read out operation. Read out operation will be described with reference to FIG.
12
.
When stabilization of the above-described precharge state is achieved, precharge activating signal BLEQ is pulled down to a low level, whereby NMOS transistors
8
,
9
,
10
and
11
are inactivated. As a result, the pair of bit lines BL, /BL attain a floating status at precharge potential.
When word line WL is activated to have potential VBL raised, charge representing data stored in memory cell
1
is transmitted on bit line BL. This is the transmission operation of data. If memory cell
1
stores data “1”, for example, potential VBL of bit line BL becomes slightly higher than the precharge potential. Bit line /BL remains at the precharge potential. Therefore, there is a slight potential difference between bit lines BL and /BL.
When such a potential difference is generated, this potential difference is amplified by the amplify operation of first and second sense amplifiers SA
1
and SA
2
. In the amplify operation, first an amplification by the first amplifier SA
1
is carried out. Sense operation activating signal SON is activated to attain a high level, whereby NMOS transistor
12
is activated. This causes shorting between outgoing line node Z and ground node
11
, whereby potential VZ of outgoing line node Z is decreased towards ground potential GND.
As a result, NMOS transistors
4
and
5
have their gate-source voltages increased to be activated. When NMOS transistors
4
and
5
are activated, the on resistance of NMOS transistor
5
becomes lower than that of NMOS transistor
4
due to potential VBL of bit line BL being higher than potential V/BL of bit line /BL, whereby potential V/BL of bit line /BL is reduced.
Next, amplification by second sense amplifier SA
2
is carried out. Sense operation activation signal SOP is activated to attain a low level, whereby PMOS transistor
14
is activated. This causes shorting between supply line node Y and power supply node
13
, whereby potential VY of supply line node Y is increased towards power supply potential Vcc.
As a result, PMOS transistors
6
and
7
have their gate-source voltages increased to be activated. When PMOS transistors
6
and
7
are activated, the on resistance of PMOS transistor
6
becomes smaller than that of PMOS transistor
7
due to potential V/BL of bit line /BL being lower than potential VBL of bit lines BL. Therefore potential VBL of bit line BL increases.
Then, potential V/BL of bit line /BL is reduced to the level of ground potential GND, and potential VBL of bit line BL is increased to the level of power supply potential VCC. By the above-described amplify operation, a slight potential difference between bit lines BL and /BL is amplified to a greater level.
At the start of an amplify operation, the source potentials of NMOS transistors
4
and
6
attain a precharge potential, as described above. The substrate potential is generally ground potential GND or lower thereof, i.e. a potential lower than the source potential. Therefore, NMOS tra

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