Use of an insulating spacer to prevent threshold voltage...

Details Use of an insulating spacer to prevent threshold voltage... Use of an insulating spacer to prevent threshold voltage...

1999-11-02

2001-06-26

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S221000, C438S296000, C438S426000, C257S510000

Reexamination Certificate

active

06251747

ABSTRACT:

FIELD OF INVENTION
The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to a process to maintain the integrity of the shallow trench isolation regions during etch of the fill dielectric regions.
BACKGROUND OF INVENTION
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-function devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices has been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS, n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
One important step in the manufacture of such devices is the formation of isolation areas to electrically separate the electrical devices or portions thereof, that are closely integrated in the silicon wafer. While the particular structure of a given active device can vary between device types, a MOS-type transistor generally includes source and drain regions and a gate electrode that modulates current flowing in a channel between the source and drain regions. Unintended current should not flow between the source and drain regions of adjacent MOS-type transistors. However, during the manufacturing process, movement of dopant atoms, for example, of boron, phosphorus, arsenic, or antimony, can occur within the solid silicon of the wafer. This movement is referred to as diffusion. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and those dopant atoms within the silicon wafer. Diffusion processes at elevated temperatures are typically utilized when forming p-type and n-type regions of a silicon integrated circuit device.
A technique referred to as “trench isolation” has been used to limit such flow. A particular type of trench isolation is referred to as shallow trench isolation (STI). STI is often used to separate the respective diffusion regions of devices of the same or opposite polarity type (i.e., p-type versus n-type).
In forming the STI regions, one technique involves the layering of dielectric films on a silicon substrate. A prior art process begins with a silicon substrate, upon which a thin layer of silicon dioxide is formed. In an example process, about 100 Å of SiO
2
is deposited on the silicon substrate. Following the oxide deposition, a substantially thicker layer of silicon nitride is deposited upon the thin oxide layer. In the example process, the process deposits about 1800 Å silicon nitride. Through photolithography, the STI regions are masked with a photoresist. An etch selective to the SiN/SiO
2
stack is performed until the silicon substrate is exposed. The photoresist mask is then stripped off. Using the SiN as a mask, the process etches shallow silicon trenches into the substrate. The opened trenches typically receive a fill deposition of high-density plasma (HDP) oxide. In an example process, oxide is deposited at a thickness of between about 6000 Å to 9000 Å to fill trenches whose depths range from about 2500 Å to 3500 Å. A planarization process is then used to remove excess oxide. The remaining silicon nitride is used as an etch stop. In a modern sub-micron process, chemical-mechanical polishing (CW) is used to planarize the features.
Referring to
FIG. 1A
of a prior art process, the features are shown after having undergone CMP. Device
100
is formed on a substrate
110
. STI regions
150
are separated by the SiO
2
/SiN stacks
140
. The stack
140
consists of the thin oxide layer
120
and a nitride layer
130
. Following the planarization, the nitride is stripped with a wet cleaning process. The areas of stripped nitride can be used to provide regions of active areas separated by STI. Next, post CMP cleaning processes and a “sacrificial oxidation” pre-clean process step followed by growth of about 200 Å to 300 Å sacrificial oxidation layer prepares the active areas of the MOS transistor structure for subsequent processing.
The preceding processes may form STI oxide recesses near the top comers of the trenches. This is a significant challenge to overcome. Referring to
FIG. 1B
, the oxide recesses
160
are shown. These recesses cause a V
t
roll-off in narrow transistors, also known as the wrap around effect, owing to the gate oxidation thinning in subsequent processing and the higher electric field around the sharp top comers of the trenches near the active area
120
a
. Consequently, the top comer oxide recess enhances the wrap around effect and degrades the transistor performance of a device built in the active area
120
a.
Accordingly, there is a need for a process that minimines the likelihood of forming such recesses that tend to degrade transistor performance.
SUMMARY OF INVENTION
The present invention is exemplified in a number of implementations, one of which is sununarized below. The invention minimizes the formation of recesses in the STI structure during processing. According to one embodiment, a semiconductor substrate has at least one shallow trench separated from other devices by formed insulating regions, which later define active transistor areas of an integrated circuit. A method of forming an insulating spacer comprises depositing a dielectric over the substrate and substantially filling in the trench regions and covering the insulating regions. Next, the method planarizes the dielectric so that it is substantially flush with the insulating regions. The insulating regions are formed by masking the dielectric disposed over the trench regions substantially covering the dielectric and overlapping at least a portion of the insulating regions. Unmasked portions of the insulating regions are removed and the insulating spacers remain. The unmasked portions of the insulating regions define the active transistor areas. Next, the active transistor areas are cleaned and a sacrificial oxide layer is grown therein. After growing the sacrificial oxide layer, the insulating spacers are removed.
The above summary of the present invention is not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follows.


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patent: 224039 (1987-06-01), None
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