Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-10-15
2001-08-14
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S168000, C711S210000, C710S005000
Reexamination Certificate
active
06275913
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to memory architectures for computer systems. More specifically, the present invention relates to a method and an apparatus for preserving the ordering of memory requests directed to multiple memory controllers.
2. Related Art
As computer systems grow increasingly more sophisticated, they are beginning to include multiple functional units. For example, it is common for a computer system to include one or more central processing units (CPUs) as well as a graphics processor and various DMA devices. As the number of functional units in a computer system increases, the computer system's memory comes under increasing pressure to service memory requests. Consequently, the memory can become a bottleneck to computer system performance.
One solution to this problem is to incorporate multiple memory channels in a computer system, wherein each memory channel handles accesses to a different region of memory. These multiple memory channels can work in parallel to service memory requests from the multiple functional units.
In designing a system with multiple memory channels, it is important to allow each functional unit to access to all of the memory channels, so that each functional unit can access all of the regions of memory. One problem in doing so is that memory requests from a given functional unit may return out of order from different memory controllers. This can create problems if there are dependencies between the memory requests. One solution to this problem is to provide additional circuitry at the functional unit to ensure that memory requests are executed in order. However, this complicates the design of the functional unit and may limit the performance advantages of queuing requests at memory controllers.
Another solution is to include circuitry within the memory controllers to ensure that requests from a given functional unit are issued in order. This simplifies the design of functional units and can improve overall computer system performance. However, this requires the memory controllers to communicate information with each other, which can cause prohibitively large communication delays.
What is needed is a method and an apparatus that enables multiple memory controllers to ensure that requests from functional units are issued in order without incurring large communication delays.
SUMMARY
One embodiment of the present invention provides a method for preserving ordering of memory requests distributed across multiple memory controllers. This method operates within a system that receives a memory request at a first memory controller. This memory request includes a source tag indicating a source from which the memory request originated. (For example, a source tag may identify a processor or a graphics accelerator.) Next, the system compares the source tag with source tags for pending memory requests in a second memory controller to determine if the second memory controller contains any pending memory requests from the same source. Note that the source tags for the second memory controller are stored within the first memory controller. If the second memory controller contains pending memory requests from the same source, the system prevents the memory request from issuing from the first memory controller until the pending memory requests from the same source within the second memory controller complete. Finally, the system issues the memory request from the first memory controller to a first random access memory coupled to the first memory controller.
In one embodiment of the present invention, the system additionally propagates the source tag for the memory request to the second memory controller so that the second memory controller can compare source tags for subsequent requests received at the second memory controller against source tags for pending memory requests in the first memory controller. In a variation on this embodiment, the system stores the source tag in a FIFO circuit in the second memory controller.
In one embodiment of the present invention, the system additionally compares the source tag with source tags for pending memory requests in a third memory controller to determine if the third memory controller contains any pending memory requests from the same source. If the third memory controller contains pending memory requests from the same source, the system prevents the memory request from completing until the pending memory requests from the same source within the third memory controller complete.
In one embodiment of the present invention, the system prevents the memory request from completing by stalling the first memory controller until the pending memory requests within the second memory controller from the same source complete. In a variation on this embodiment, stalling the first memory controller includes stalling pending memory requests in the first memory controller.
In one embodiment of the present invention, comparing the source tag with the source tags for pending memory requests in the second memory controller further comprises comparing a time stamp associated with the memory request against time stamps associated with the pending memory requests in the second memory controller.
In one embodiment of the present invention, the system additionally receives a response from the first random access memory indicating that the memory request has been completed. If the memory request is a read operation, the system returns the read data to the source from which the memory request originated.
REFERENCES:
patent: 4733352 (1988-03-01), Nakamura et al.
patent: 5442755 (1995-08-01), Shibata
patent: 5603005 (1997-02-01), Bauman et al.
patent: 6167492 (2000-12-01), Keller et al.
Kim Matthew
Micro)n Technology, Inc.
Park Vaughan & Fleming LLP
Tran Denise
LandOfFree
Method for preserving memory request ordering across... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for preserving memory request ordering across..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for preserving memory request ordering across... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2449435