Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1997-07-11
2001-01-09
Utech, Benjamin (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S712000, C438S717000, C438S736000
Reexamination Certificate
active
06171967
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a self-aligned metal wire of a semiconductor device, and more particularly to a method for forming a self-aligned metal wire of a semiconductor device which prevents the surface of a contact hole from being reduced due to an erroneous alignment of a trench for forming the contact hole and upper layer wiring.
2. Discussion of Related Art
In general, aluminum or aluminum alloy film has high electrical conductivity, excellent adhesion to silicon oxide film, is easily patterned through dry etching, and also has a relatively low cost. Such films have been widely used as the circuit metal wiring in a semiconductor device. However, since the metal wiring becomes fine and multilayered as the size of the semiconductor device is reduced to increase the density thereof, the topography of a surface where the metal wiring is to be formed deteriorates. Alternatively, stepcoverage at an angle or bent portion, such as the inside of a contact hole, becomes emphasized. That is, when forming the metal wiring film by sputtering aluminum or aluminum alloy film through a conventional method, the thickness of the metal wiring film becomes particularly thin at the angle portion due to the shadow effect. More particularly, this phenomenon seriously occurs in contact holes with an aspect ratio larger than one.
Accordingly, instead of a physical deposition method such as sputtering, studies have been performed to improve stepcoverage by using the chemical vapor deposition method (CVD) which is capable of flattening a surface of the film to be formed.
As the width of the metal wiring becomes very fine with the increased density of the semiconductor device, the metal wiring has to be formed with a metal having a higher electrical conductivity than aluminum or aluminum alloy such as copper (Cu), gold (Au) and silver (Ag). Since copper has excellent electro-migration and stress migration characteristics as well as lower resistivity as compared with aluminum, metal wiring formed with copper has enhanced reliability. Thus, a method of forming metal wiring film of copper by sputtering or by CVD has been studied.
However, when etching copper using a halogen chemical compound, usually used to etch aluminum, the temperature has to be increased to a high temperature of about 500° C. because the vapor pressure of halogen chemical compounds is low.
Accordingly, a method of directly patterning the copper wiring through etching is not used. Instead, a method of making a buried conductor by performing an etchback through chemical mechanical polishing (CMP), after (1) forming a trench structure corresponding to the desired metal wiring pattern on the substrate and (2) depositing copper thin film, is being studied. Furthermore, techniques of multi-wiring by (1) aligning (a) the contact hole for connecting lower wiring and upper wiring and (b) the trench for forming the upper wiring, and (2) connecting the lower wiring and the upper wiring through the contact hole upon formation of upper wiring have been published in VMIC (p.144-p152) by IBM Inc., on 1991, entitled “Dual Damascene: A ULSI Wiring Technology”, and in an IEDM (p.305-p308) by NEC Inc., entitled “A Quarter-Micron Planarized Interconnection Technology With Self-Aligned Plug”.
FIGS. 1A
to
1
D are provided for explaining a method of forming a self-aligned metal wire of a semiconductor device in accordance with the above-cited technique published by IBM Inc.
Referring to
FIG. 1A
, a first insulator film
13
is formed on a semiconductor substrate
11
, and a first conductive layer
15
is formed on the first insulator film
13
. Then, the first conductive layer
15
is longitudinally pattered through a conventional photolithography method, and a second insulator film
17
is formed on the first insulator film
13
and the first conductive layer
15
. Next, a first photosensitive film
19
is deposited on the second insulator film
17
, and then exposed and developed to expose the second insulator film
17
where a contact hole is to be formed. A second photosensitive film
21
is deposited on the exposed part of the second insulator film
17
and the first photosensitive film
19
, and is longitudinally exposed and developed in a length direction of the first conductive layer
15
. At this time, a developed part of the second photosensitive film
21
, i.e., a trench pattern for forming an upper conductive layer, includes part of the exposed second insulator film
17
and an undeveloped portion of the first photosensitive film
19
.
In
FIG. 1B
, the exposed part of the second insulator film
17
is anisotrophy-etched to a given depth using the first and second photosensitive films
19
and
21
as a mask to form the contact hole
23
. The contact hole
23
is formed so that the first conductive layer
15
is not exposed.
As shown in
FIG. 1C
, the second and the first photosensitive films
21
and
19
are sequentially etchbacked to transfer the trench pattern of the second photosensitive film
21
to the first photosensitive film
19
. Then, the exposed part of the first photosensitive film
19
is removed so that the second insulator film
17
may be exposed. Accordingly, the second insulator film
17
is longitudinally exposed in a length direction of the first conductive layer
15
. The second insulator film
17
is anisotrophy-etched with the second and first photosensitive films
21
and
19
as the mask to form the trench
25
. At this time, a bottom surface of the contact hole
23
is etched so that the first conductive layer
15
is exposed by the contact hole
23
.
Regarding
FIG. 1D
, after the first and the second photosensitive films
19
and
21
are removed, conductive material such as copper etc., with which the contact hole
23
and the trench
25
are filled, is deposited on the second insulator film
17
so as to be electrically connected to the first conductive layer
15
and to form a second conductive layer
27
. The second conductive layer
27
deposited on the second insulator film
17
is then etchbacked through the chemical mechanical polishing CMP method.
FIGS. 2A
to
2
D are provided for explaining a method of forming a self-aligned metal wire of a semiconductor device in accordance with the conventional technique described by NEC Inc.
Referring to
FIG. 2A
, the first insulator film
13
is formed on the semiconductor substrate
11
, and the first conductive layer
15
is formed on the first insulator film
13
. The first conductive layer
15
is longitudinally patterned by the conventional photolithography method, and the second insulator film
17
is formed on the first insulator film
13
and the first conductive layer
15
.
In
FIG. 2B
, another insulating material whose etching select ratio is different from that of the first insulator film
13
is deposited on the second insulator film
17
to form an etching protection layer
18
. The first photosensitive film
19
is deposited on the etching protection layer
18
, and then exposed and developed to expose the etching protection layer
18
where the contact hole is to be formed. Further, the second insulator film
17
is exposed by etching the exposed part of the etching protection layer
18
using the first photosensitive film
19
as a mask.
As to
FIG. 2C
, the first photosensitive film
19
is removed and then, a third insulator film
20
is formed on the second insulator film
17
and the etching protection layer
18
using the same insulating material as the second insulator film
17
. The second photosensitive film
21
is deposited on the third insulator film
20
and is longitudinally exposed and developed in a length direction of the first conductive layer
15
. At this time, the developed part of the second photosensitive film
21
, which has the trench pattern for forming the upper conductive layer, includes the exposed part of the second insulator film
17
and exposes a portion of the third insulator film
20
. The exposed part of the third insulator film
Deo Duy-Vu
LG Semicon Co. Ltd.
Utech Benjamin
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