Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1998-12-08
2001-01-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
C427S578000, C427S579000, C118S715000
Reexamination Certificate
active
06174743
ABSTRACT:
TECHNICAL FIELD
The present invention relates, generally, to semiconductor fabrication, and more particularly to methods for forming improved inter-layer dielectric (ILD) coatings for semiconductor substrates having small gaps between electrically conducting interconnect lines.
BACKGROUND
Semiconductor microchips find use in a wide variety of applications, including hand-held computing devices, wireless telephones, desktop computers, and digital cameras, etc. These microchips are generally comprised of logic and memory devices. It is important and desirable that each semiconductor microchip contain as many logic or memory devices as possible per unit area. This effectively reduces the size, weight, and energy consumption of devices formed on the wafers. At the same time, the memory capacity and computing power of the devices is improved.
As stated above, semiconductor devices are divided into two very broad categories, logic devices and memory devices. The present invention is applicable to either of these general categories. The microcircuit structures formed in present art fabrication processes are electrically interconnected by conductive elements referred to as “interconnect lines”. Typical interconnect lines are formed by the deposition of one or more electrically conductive layers (also commonly known as metallization layers) on a substrate followed by lithographic masking according to a predetermined pattern and etching to transfer the lithographic pattern onto the conducting layers. These etched patterns form interconnect lines which may be arranged in multi-level structures through repeated process steps. After etching, the interconnect lines are electrically isolated from each other by depositing dielectric material in the open spaces separating the interconnect lines as well as between the various vertical layers of multi-layer structures. The process of electrically isolating these interconnects is known as forming an inter-layer dielectric (ILD).
With the increasing circuit density of modern integrated circuits came the need for increasing interconnect density. Interconnect lines became thinner and more closely spaced in order to accommodate the need of increasing circuit density. Keeping this in mind, the so-called 0.25 &mgr;m technology was developed. In 0.25 &mgr;m technology, the transistor gates are approximately 0.25 &mgr;m wide and the spacing between interconnect lines is generally less than about 0.35 &mgr;m. At the same time, the interconnect lines have heights in the range of about 0.7 &mgr;m to about 1.1 &mgr;m. These small sizes result in advantageous increases in circuit density. However, the small size of 0.25 &mgr;m technology makes the formation of a reliable ILD layers difficult.
Typical interconnect lines are formed on top of a substrate using a “stack” of more than one material. Such stacks are typically formed of several layers, for example, an aluminum or aluminum alloy layer and one or more other layers. A typical stack may have a thin titanium (Ti) layer, followed by the deposition of a thin aluminum (Al) layer, which is then capped with a thin titanium nitride (TiN) layer. Although the foregoing example uses a three layer TiN/Al/Ti stack, stacks may be formed using more (or fewer) layers and many different combinations of materials. The specific materials chosen are selected by process engineers to meet preset specifications. These metallization layers are lithographically patterned and chemically etched to form the desired pattern for the interconnect lines. In accordance with current technology, the gaps between the adjacent metal stacks are filled with an electrically insulating material to form an ILD. Commonly employed methods use high density plasma (HDP) deposition or plasma-enhanced chemical vapor deposition at temperatures in excess of 400° C. Unfortunately, these high process temperatures cause some significant problems.
As linewidths and feature sizes have decreased and interconnect density has increased over the past ten years, a phenomenon known as “stress-induced voiding” or “cavitation” has become common. Voids in interconnect lines degrade microcircuit performance, eventually leading to microcircuit failure. In the recent past, metal interconnect linewidths were relatively large, as a result, the occurrence of stress-induced voiding was infrequent. However, as interconnect linewidth has decreased, the incidence and magnitude of stress-induced voiding has become significant.
The problem of stress-induced voiding has its roots in the differing rates of thermal expansion existing between interconnect materials, the substrate materials, and ILD materials. The thermal expansion coefficients of conducting materials may be five times or more as great as the thermal expansion coefficients of the silicon and ILD materials which encase them. The conducting material expands and contracts at a different rate than the surrounding semiconductor and dielectric materials. This becomes a problem during the heating and cooling cycles of semiconductor fabrication processes. A more complete description of these problems and their drastic effect on interconnect lines is set forth in “Stress-Induced Void Formation in Metal Lines”, M.R.S. Bulletin, December 1993, by Paul A. Flinn, Anne Sauter Mack, Paul R. Besser, and Thomas N. Marieb, the text of which is hereby incorporated, in its entirety, by reference.
During heating and cooling, the stack materials expand and contract at a greater rate than either the silicon or the dielectric layers which confine them. This causes stress in the interconnect lines. Once the stress becomes too great, the interconnect material plastically deforms in order to relieve the stress. This level of stress is known as the yield stress of the material. Generally speaking, when a material is subject to stress in one or two directions it deforms and undergoes plastic flow in the unstressed directions to relieve the stress. However, when confined by relatively rigid structures, as is the case when interconnect lines are surrounded by the substrate and an ILD layer, the interconnect can not plastically flow. In microcircuit interconnects, this may result in voiding. The effects of voiding in interconnect lines are compounded by an effect known as “void electromigration” which causes the voids to move and aggregate causing circuit failure. These effects may be intensified by process conditions which lead to embrittlement of the interconnect materials, making them more vulnerable to the voiding phenomena.
For the forgoing reasons there is a need for ILD fabrication methods and structures which reduce embrittlement of interconnect lines and reduce the incidence of stress-induced voiding in interconnect lines.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for fabricating and electrically isolating electrical interconnect lines on a semiconductor substrate. The method includes providing at least one substrate (typically, a silicon wafer), and establishing a predetermined pattern of electrical interconnect lines on the substrate. In accordance with the principles of the invention, a silicon oxynitride (SiON) dielectric layer is deposited between, and on top of, said interconnect lines. A second silicon dioxide (SiO
2
) layer is then formed over the SiON layer. These two layers form an ILD. A SiON layer is formed by using plasma-enhanced chemical vapor deposition of a silicon oxynitride layer between, and on top of, said electrical interconnect lines, said deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, said gases being dispensed at regulated flow rates and being energized by a radio frequency power source to form said plasma. The plasma reacts to form SiON. The SiON material is deposited on the interconnect lines by moving the substrate into the plasma cloud where a SiON layer deposits on the wafer surface. By carefully regulating and reducing the process temperatures to less than about 380 degrees Celsius (° C.) during SiON deposition, the incidence of stress-induced voiding in the underl
Besser Paul R.
Ngo Minh Van
Pangrle Suzette K.
Advanced Micro Devices , Inc.
Bowers Charles
Kielin Erik J
LaRiviere Grubman & Payne, LLP
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