Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-24
2001-06-19
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C257S410000, C257S412000
Reexamination Certificate
active
06249021
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same. More particularly, the present invention pertains to a nonvolatile semiconductor memory device featuring performance of flash erasure of memory transistors and reduced variation in erase operation time, and a manufacturing method thereof.
BACKGROUND OF ART
A flash-type EEPROM contains a multiplicity of memory transistors.
FIG. 16
shows a schematic sectional view of one of these memory transistors. A memory transistor
200
comprises a source region
55
and a drain region
56
, which are impurity diffusion layers formed in a semiconductor substrate
50
, and a tunnel oxide film
51
, a floating gate
52
, a dielectric layer
53
, and a control gate
54
which are layered on the semiconductor substrate
50
. On the side areas of the layered floating gate
52
, dielectric layer
53
and control gate
54
, there is provided a side wall
57
made of an insulating material.
In the memory transistor
200
, information is programmed by injecting electrons
58
into the floating gate
52
(which is a write operation, indicated by an arrow
59
in
FIG. 16
) and by drawing the electrons from the floating gate
52
(which is an erase operation, indicated by an arrow
59
′ in FIG.
16
).
In the flash-type EEPROM, an erase operation is performed on a plurality of memory transistors entirely. In most cases, erasure is carried out on the entire EEPROM or on each page corresponding to a group of plural memory transistors. For example, an erase operation is accomplished as described below.
A source voltage Vs, which is a high potential (e.g., 12 V), is applied to the source region
55
. At this step, the control gate
54
and the semiconductor substrate
50
have a ground potential, and the drain region
56
is open. In this state, electrons
58
stored in the floating gate
52
are drawn into the source region
55
through the thin tunnel oxide film
51
by means of the Fowler-Nordheim tunnel, as indicated by the arrow
59
′ in FIG.
16
. This results in a threshold voltage Vg of the memory transistor
200
being equal to a threshold voltage level of a common MOS transistor.
In the flash-type EEPROM used as a storage device, it is desirable that the erase operation mentioned above should be carried out at higher speed. Namely, a period of time required for a flash erase operation (i.e., an erase characteristic) is of critical importance in the flash-type EEPROM.
Further, the erase characteristic is required to be uniform among respective memory elements. If the erase characteristic is not uniform among the memory elements, a malfunction may occur in the memory element to cause various problems as mentioned below.
For instance, when the time required for erasure in some memory transistors is longer than a predetermined erase operation time, electrons remain stored in the floating gates of these memory transistors. This condition is called “under-erasure”. On the contrary, when the time required for erasure in some memory transistors is shorter than a predetermined erase operation time, electrons are drawn excessively from the floating gates of these memory transistors. This condition is called “over-erasure”.
In the case where the degree of variation in the erase characteristic is small among the memory transistors, it is possible to select an erase operation time “T” that allows proper erasure of any memory transistors. However, in case that the degree of variation in the erase characteristic is large, there is a substantial possibility that under-erasure or over-erasure may occur at some cells. Further, in the case where the degree of variation in the erase characteristic is extremely large, under-erasure or over-erasure will occur inevitably in some memory transistors, no matter what erase operation time “T” maybe selected. Thus, it becomes impossible to perform proper erasure in any memory transistors.
For realizing a high-speed flash-type EEPROM, it is required to decrease the erase operation time “T” insofar as possible. Since erasure is performed by drawing electrons from the floating gate
52
to the source region
55
as described above, a higher-speed erase operation may be achieved by increasing an overlapping area of the floating gate
52
and the source region
55
. When the overlapping area is too large, however, a problem such as a malfunction may be prone to occur.
Therefore, for a realization of the high-speed flash-type EEPROM, it is required to increase the overlapping area of the source region and floating gate to the extent that no malfunction will occur, while minimizing the degree of variation in the overlapping area among respective memory transistors.
DISCLOSURE OF THE INVENTION
It is an object of the present invention to provide a nonvolatile semiconductor memory device comprising a memory transistor having a uniform erase characteristic to enable high-speed flash erasure, and a method of manufacturing the same.
As one aspect of the present invention, there is provided a nonvolatile semiconductor memory device, comprising:
a semiconductor substrate; and
a memory transistor including a source region and a drain region which are impurity diffusion layers formed in the semiconductor substrate, a tunnel insulating layer formed on the semiconductor substrate, and a gate electrode of a stacked structure having a floating gate, a dielectric layer and a control gate which are layered on the tunnel insulating layer,
wherein the floating gate is formed of a polysilicon layer having an impurity concentration of 1×10
19
to 1×10
20
cm
−3
.
In the nonvolatile semiconductor memory device mentioned above, since an impurity concentration of the polysilicon layer constituting the floating gate is in a specified range, deterioration of the film quality of the tunnel insulating layer due to impurities contained in the floating gate can be prevented, and it is possible to improve an erase characteristic and a data retaining characteristic. Further, the impurity concentration of the polysilicon layer constituting the floating gate is preferably in a range of 1×10
19
to 5×10
19
cm
−3
.
Denoting the impurity concentration of a first polysilicon layer constituting the floating gate as C
FG
and the impurity concentration of a second polysilicon layer constituting the control gate as C
CG
, it is preferable that the following relational expression be satisfied:
0.3×C
FG
≦C
CG
≦0.8×C
FG
By setting up the above relationship, the impurity concentrations of the polysilicon layers constituting to the floating gate and the control gate approximate each other. Consequently, in forming an electrode comprising the floating gate, dielectric layer, and control gate by means of etching, the end portion of each layer can be aligned in the thickness direction to allow formation of an ideal stacked-structure gate electrode. According to the inventors of the present invention, it has been confirmed that such an ideal stacked gate structure greatly contributes to an improvement in the data retaining characteristic, for example.
In the source region, an overlapping region with the floating gate is preferably 25 to 45% of a bottom surface of the floating gate. A high-speed erasure can be possible by such an arrangement that the source region and the floating gate are formed to sufficiently overlap each other to the proper extent that a malfunction can be prevented.
Further, the source region preferably comprises a first diffusion region having a high impurity concentration, and a second diffusion region disposed outside the first diffusion region and having an impurity concentration lower than that of the first diffusion region. In such an arrangement that the source region is formed in a double diffusion structure, it becomes possible to control the transfer rate of electrons to move from the floating gate to the source region.
As another aspect of the present invention, there is provided a method of manufact
Oliff & Berridg,e PLC
Seiko Epson Corporation
Wojciechowicz Edward
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