Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-23
2001-04-10
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S344000, C257S204000, C438S376000, C438S546000, C438S501000, C438S199000, C438S217000
Reexamination Certificate
active
06215151
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of forming integrated circuitry and to related integrated circuitry.
BACKGROUND OF THE INVENTION
An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers. Integrated circuitry can employ different types of MOS structures or transistors which are formed on a common substrate. NMOS transistors include source/drain diffusion regions which comprise an n-type dopant. PMOS transistors include source/drain diffusion regions which comprise an p-type dopant. CMOS (complementary metal-oxide-semiconductor) is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of produced holes or electrons.
NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functionally dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS represented a lower-power technology capable of exploiting large scale integration fabrication techniques.
CMOS fabrication does however present a number of challenges to the fabricator as compared to using PMOS or NMOS alone. Specifically, typically independent or separate masking steps are utilized for masking one of the p-type regions while the n-type region is being doped. Also, the n-type regions are separately masked when the p-type regions are being doped. Accordingly, typical transistor flows use one mask each to form the n-channel and p-channel transistor source and drain regions. Higher levels of integration result in denser and denser circuits, leading CMOS fabrication to more difficulties. One manner of simplifying transistor flows has been to combine masking steps. This in itself presents unique challenges which this invention addresses.
It would be desirable to develop methods which further facilitate formation of integrated circuitry devices. It would also be desirable to develop methods which further facilitate formation of NMOS and PMOS devices.
SUMMARY OF THE INVENTION
Integrated circuitry and methods of forming integrated circuitry are described. In one implementation, a common masking step is utilized to provide source/drain diffusion regions and halo ion implantation or dopant regions relative to the source/drain regions within one well region of a substrate; and well contact diffusion regions within another well region of the substrate. The common masking step preferably defines at least one mask opening over the substrate within which the well contact diffusion region is to be formed, and the mask opening is suitably dimensioned to reduce the amount of halo ion implantation dopant which ultimately reaches the substrate therebelow. According to one aspect, a plurality of mask openings are provided. According to another aspect, a suitably-dimensioned single mask opening is provided. In yet another aspect, a unique well region construction is provided with one or more complementary mask openings which is (are) configured to, in connection with the provision of the halo ion implantation dopant, block the amount of implantation dopant which ultimately reaches the substrate adjacent the well contact diffusion regions. Accordingly, at least some of the well contact diffusion region(s) remain in substantial contact with the well region after the doping of the substrate with the halo ion implantation dopant.
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Batra Shubneesh
Kerr Robert
Tran Luan C.
Wu Zhiqiang
Yang Rongsheng
Lee Jr. Granvill D
Micro)n Technology, Inc.
Smith Matthew
Wells, St. John, Roberts Gregory & Matkin P.S.
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