Method of fabricating self-aligned polysilicon via plug

Details Method of fabricating self-aligned polysilicon via plug Method of fabricating self-aligned polysilicon via plug

2000-06-26

2001-09-18

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S398000

Reexamination Certificate

active

06291338

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for a via plug. More particularly, the invention relates to a method of fabricating a self-aligned polysilicon via plug.
2. Description of Related Art
As the semiconductor technology progresses, the device keeps downsizing for entry into the deep micron process. While the integration of the device increases, it becomes less possible to provide sufficient area for fabricating required interconnects. In order to satisfy an increased need for interconnects after the size of the device is minimized, it is desirable to design multilevel interconnects with two or more layers in the very large scale integration (VLSI) technology. Also, it is necessary to form a hole, such as via hole in the insulating layer between two metal layers, and to fill the via hole with a conductive material so as to provide a connection between different metal layers.
As the demand for highly integrated device increases, it implies that the device need to be made more compact, with a smaller metal line and via plug or metal plug. Accordingly, a contact area between the via plug and the metal line becomes smaller. Moreover, in the conventional semiconductor process, the metal layer and the via opening are patterned using a photolithography and etching process. Therefore, once a misalignment occurs during the photolithography and etching process, the contact area between the via plug and the metal line is further reduced. It is known by those skilled in the art that a reduction in contact area between the via plug and the metal line creates a large local current density when the current flows through a junction between the metal line and the via plug. This leads to an electro-migration (EM) which reduces reliability of the device, and even results an open circuit in a worse scenario. The EM occurs as a result of electrons from the current that flowing through the metal line and bombarding a surface of the metal grains to break open connected metal grains. Thus, this leads to an open circuit. As the integration increases, together with a very large misalignment, the open circuit problem becomes more serious while the production yield is greatly reduced.
To better understand the problems caused by downsizing of the device, reference is made to
FIGS. 1A through 1C
, which illustrate a conventional process for fabricating a DRAM device.
Referring to
FIG. 1A
, a via opening
110
is formed on a dielectric layer
100
.
Referring to
FIG. 1B
, a conductive layer
120
, such as polysilicon layer or polycide layer is formed on the dielectric layer
100
so as to fill the via opening
110
with the conductive layer
120
. The method for forming the conductive layer
120
includes chemical vapor deposition (CVD).
Referring to
FIG. 1C
, the conductive layer
120
is patterned to form a via plug
130
, followed by forming a metal line
140
thereon.
The metal line
140
and the via opening
110
are patterned by a photolithography and etching process. Once a misalignment occurs, a contact area between the via plug
130
and the metal line
140
is reduced as shown in FIG.
1
C. As the contact area between the via plug and the metal line is reduced, a large local current density is created when the current flows through a junction between the metal line and the via plug. This leads to an electro-migration (EM) which reduces reliability of the device, and even results an open circuit in a worse scenario.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a self-aligned polysilicon via plug, in order to increase a contact area between the via plug and a metal line even if a misalignment occurs in the conventional process.
According to another aspect of the invention, a fabrication method for the via plug prior to formation of the metal line is provided. The method includes forming the via plug in a self-aligned manner below the metal line, such that a contact area between the via plug and the metal line is equal to an area of the contact opening.
The invention further provides a method of fabricating a self-aligned polysilicon plug in order to provide highly reliable metal interconnects. Therefore, the integration of the device is increased in the deep micron process while a high production yield is maintained.
As embodied and broadly described herein, the invention provides a fabrication method for the polysilicon via plug, which method involves forming a first polysilicon layer on a first silicon layer. A second silicon oxide layer is then formed on the first polysilicon layer, followed by forming a first photoresist layer on the second silicon oxide layer by coating. A first opening is formed on the second silicon oxide layer by patterning the first photoresist layer using a dry etching process prior to removing of the first photoresist layer. The first opening is then filled with a second polysilicon layer. A second photoresist layer is formed on the second silicon oxide layer and the second polysilicon layer. The second photoresist layer is patterned to form a second opening which exposes a part of the second polysilicon layer and a part of the second silicon oxide layer, wherein the second opening is perpendicular to the second polysilicon layer. With the patterned second photoresist layer and the second silicon oxide layer serving as a mask, the exposed part of the second polysilicon layer and a part of the first polysilicon layer are removed to form a third opening which exposes a part of the first silicon oxide layer.
The second photoresist layer and the second silicon oxide layer are removed. With the first polysilicon layer and the second polysilicon layer serving as a mask, the exposed part of the first silicon oxide layer is removed to form a fourth opening. A third polysilicon layer is formed on the first polysilicon layer and the second polysilicon layer so as to fill the via opening. With the first silicon oxide layer serving as an etching stop, an anisotropic etching process is performed to remove the third polysilicon layer, the first polysilicon layer, and the second polysilicon layer until the first silicon oxide layer is exposed. Accordingly, a via plug is formed in the first silicon oxide layer, with a portion of the via plug above the first silicon oxide layer forms a conductive line.
In the method of fabricating the conductive line, the first opening is formed before filling the first opening with the polysilicon layer to form a metal damascene. After the second dielectric layer and the first polysilicon layer are removed, the via opening is formed to reduce an aspect ratio during the formation of the via plug. Thus, the formation of the via plug is greatly improved.
According to the present embodiment, the sequence of steps involved in the conventional process is modified together with a selective etching process for polysilicon/silicon oxide, whereby a opening is formed to expose the IPD layer. Furthermore, a selective etching process for silicon oxide/polysilicon, so that a via opening having its edges parallel to polycide lines is formed. A self-aligned via plug is then formed in the via opening, wherein a portion of the via plug above the first silicon oxide layer forms a part of the conductive line. Therefore, the invention provides a method of fabricating a self-aligned via plug, which improves a contact area between the via plug and the conductive line, even when a misalignment occurs in the conventional fabrication process for increasing the device integration.
In addition, the via plug is formed in a self-aligned manner below the conductive line, while the contact area between the via plug and the conductive line is equal to the area of the via opening, so highly reliable conductive lines are provided. Therefore, the integration of the device is increased in the deep micron process, as well as maintaining a high production yield.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended

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