Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2000-08-24
2001-08-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S189090
Reexamination Certificate
active
06272037
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a ferroelectric memory device and a method for generating a reference, level signal therefor. More particularly, the present invention relates to a 1T1C type ferroelectric memory, device and a method for generating a reference level signal therefor.
2. Description of the Related Art
A ferroelectric memory device includes a plurality of memory cells each of which includes a semiconductor transistor (or a switch) and a ferroelectric capacitor. The memory cells are selectively activated by selectively turning ON/OFF the semiconductor transistors. Information is stored in the memory device based on the polarity of the ferroelectric capacitor. A 1T1C type ferroelectric memory device includes a plurality of memory cells each of which includes a transistor, e.g., a MOS (Metal Oxide Semiconductor) transistor, and a ferroelectric capacitor. A potential output from a memory cell (i.e., information which has been stored in the ferroelectric capacitor of the memory cell) is compared with a reference level signal to amplify a signal corresponding to the data from the memory cell.
FIG. 7A
illustrates, in a simplified manner, a reference level generation circuit
700
of a conventional ferroelectric memory device as disclosed in Japanese Laid-Open Publication No. 10-50075. Referring to
FIG. 7A
the reference level generation circuit
700
includes two reference cells
102
and
103
. The reference cells
102
and
103
are both connected to a RWL (reference word line) signal line. The reference cells
102
and
103
are also connected to bit lines
100
a
and
100
b
, respectively. Each of the bit lines
100
a
and
100
b
crosses the RWL signal line and a BSH (bit line short) signal line. The reference level generation circuit
700
further includes a switch transistor
101
. The gate of the switch transistor
101
is connected to the BSH signal line, the source/drain of the switch transistor
101
are respectively connected to the bit lines
10
a
and
100
b
. The reference level generation circuit
700
uses two reference cells, each having the same structure as that of a memory cell in a ferroelectric memory device (not shown), for outputting an “L” level signal (data “
0
”) and an “H” level signal (data “1”), respectively. The two potentials are shorted with each other so as to generate an intermediate level between the “H” level and the “L” level, which is used as a reference level.
The generation of the reference level will be described with reference to a timing diagram shown in FIG.
7
B. Referring to
FIG. 7B
, first, a RWL signal is activated (indicated as the transition to the “H” level). Then, as illustrated in
FIG. 7A
, data obtained by inverting data “0” is output from the reference cell
102
to the bit line
100
a
, and data obtained by inverting data “1” is output from the reference cell
103
to the bit line
100
b
. While the RWL signal is activated, a BSH signal is activated (indicated as the transition to the “H” level). Thus, the reference level generation circuit
700
illustrated in
FIG. 7A
closes the switch transistor
101
so as to short the respective outputs from the reference cells
102
and
103
with each other, thereby setting the potential of each of the bit lines
100
a
and
100
b
to an intermediate level (reference level) between the “H” level and-the “L” level. After the reference level is generated, the reference level generation circuit
700
enables a sense amplifier (not shown) by activating an SAE (sense amp enable) signal (indicated as the transition to the “H” level) so as to compare the output from the selected memory cell with the reference level and amplify a signal corresponding to the output from the selected memory cell.
In this conventional example, each memory cell and each reference cell have the same structure, and a reference level is generated by shorting with each other the “H”level and the “L” level which are output from the two reference cells
102
and
103
, respectively. Therefore, the reference level is an intermediate level which is centered between the “H” level and the “L” level. However, this conventional example has a problem in that the reference cells
102
and
103
, each of which is a ferroelectric capacitor as that used in a memory cell, may deteriorate over time. Generally, a reference cell is accessed more often than a normal memory cell. Therefore, a memory device may become inoperable due to the deterioration of the reference cells even through the memory cells remain operable. This problem can be overcome by increasing the number of reference cells to be provided, which however undesirably increases the chip area.
In order to solve this problem, a ferroelectric memory device
850
having a reference level generation circuit
800
as illustrated in
FIG. 8A
has been proposed in the art. The reference level generation circuit
800
includes a reference signal generation circuit
107
, a capacitor
106
for storing a potential (level) output from the reference signal generation circuit
107
, and switch transistors
104
and
105
for controlling the capacitor
106
and the reference signal generation circuit
107
, respectively. In the reference level generation circuit
800
, the reference signal generation circuit
107
is connected to the source of the switch transistor
105
, and the drain of the switch transistor
105
is connected to the first electrode of the capacitor
106
and the source of the switch transistor
104
. The second electrode of the capacitor
106
is connected to a ground. The gates of the switch transistors
104
and
105
are connected to an RWL line and a PRC (pre-charge control) line, respectively. The drain of the switch transistor
104
is connected to a bit line
100
. The potential generated by the reference signal generation circuit
107
is charged into the capacitor
106
, and the capacitor
106
is shorted with the bit line
100
s. Thus, a potential (reference level) is generated onto the bit line
100
a
by virtue of the charge sharing between the capacitor
106
and the bit line
100
c
. A sense amplifier
15
is connected to the bit line
100
c
and also to another bit line
11
, which is connected to a memory cell
12
. The memory cell
12
includes a semiconductor transistor
16
and a ferroelectric capacitor
17
. The source of the semiconductor transistor
16
is connected to the bit line
11
, the drain of the semiconductor transistor
16
is connected to a first electrode of the ferroelectric capacitor
17
, and the gate of the semiconductor transistor
16
is connected to a word line
13
. A second electrode of the ferroelectric capacitor
17
is connected to a plate line
14
. With such a configuration, the output from the selected memory cell
12
is compared with the reference level signal to amplify the signal corresponding to the output of the memory cell
12
.
The generation of the reference level by the reference level generation circuit
800
of the ferroelectric memory device
850
illustrated in
FIG. 8A
will be described with reference to a timing diagram shown in FIG.
8
B. Referring to
FIG. 8B
, a PRC signal is activated (indicated as the transition to the “H” level) to close the switch transistor
105
so that the capacitor
106
is charged by the reference signal generation circuit
107
. Then, the PRC signal is deactivated (indicated as the transition to the “L” level), after which RWL signal is activated (indicated as the transition to the “H” level) so as to close the switch transistor
104
. Thus, a reference level is generated onto the bit line
100
c
by virtue of the charge sharing between the capacitor
106
and the bit line
100
c
. After the reference level is generated, the SAE signal is activated so as to enable the sense amplifier
15
. Thus, the output from the selected memory cell
12
is compared with the reference level signal to amplify the signal corresponding to the output of the memory cell
12
.
In the case of the reference level generati
Hoang Huan
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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