Memory cache management for isochronous memory access

Details Memory cache management for isochronous memory access Memory cache management for isochronous memory access

1998-12-29

2001-07-10

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S117000, C711S118000, C711S141000, C711S142000, C711S143000, C711S144000, C710S021000, C710S036000, C710S052000, C710S061000

Reexamination Certificate

active

06260119

ABSTRACT:

FIELD
The present invention relates to the storage of information in a computer system. More particularly, the present invention relates to memory cache management for isochronous memory access in the computer system.
BACKGROUND
Memory in a computer system can be used to store information, including, for example, information that represents audio, video and multimedia content. When a transfer of information to or from memory is “asynchronous,” delays can occur that interfere with the timely completion of the transfer. Consider, for example,
FIG. 1
, which illustrates a known architecture for connecting an external Input/Output (IO) device
10
to a computer system
100
. The computer system
100
includes a system memory
200
coupled to a memory controller
300
. The external IO device
10
communicates with the memory controller
300
, such as through an IO unit (not shown in FIG.
1
), to transfer information with the system memory
200
.
Typically, an asynchronous transfer of information from the IO device
10
to the system memory
200
may be delayed by other, more important, activities. However, even a minor delay or gap in some types of information streams will noticeably degrade the quality of the information, such as by causing a momentary freeze in a video presentation or by introducing a stuttering effect in an audio transmission.
When a transfer of information is “synchronous,” the sending and receiving devices are synchronized, such as by using the same clock signal, and the transfer of information recurs at identical periodic intervals. However, because the IO device
10
and components within the computer system
100
such as the system memory
200
, may be difficult to synchronize, a synchronous transfer of information is not appropriate in many situations.
When a transfer of information is “isochronous,” the sending and receiving devices are only partly synchronized, but the sending device transfers information to the receiving device at regular intervals. Such transfers can be used, for example, when information, such as video information, needs to arrive at the receiving device at the same rate it is sent from the sending device, but without precise synchronization of each individual data item. While a synchronous transfer of information occurs at the same time with respect to a clock signal, an isochronous transfer of information may require that up to “X” bits of data be transferred every “T” time units, although precisely when the X bits are transferred within the time T can vary. The IEEE 1394 standard (1995), entitled “High Performance Serial Bus” and available from the Institute of Electrical and Electronic Engineers, is an example of an interface that supports the isochronous transfer of information between an external IO device and a computer system.
In addition to the isochronous transfer of information between the IO device
10
and the computer system
100
, the transfer of information within the computer system
100
may also be isochronous. U.S. patent application Ser. No. 09/110,344, now U.S. Pat. No. 6,119,243 entitled “Architecture for the Isochronous Transfer of Information Within a Computer System,” to John I. Garney and Brent S. Baxter, filed on Jul. 6, 1998 discloses architectures that provide for the isochronous transfer of information within the computer system
100
.
Problems can arise, however, when isochronous information is transferred with the system memory
200
. For example, some types of IO devices, such as a Direct Memory Access (DMA) device, can manage IO traffic to and from the system memory
200
, sharing the system memory
200
with a system processor (not shown in FIG.
1
). In this case, the IO device
10
and system processor may independently access the shared system memory
200
and take turns operating on the shared data. For example, ownership of the system memory
200
may change between the IO device
10
, such as through a DMA controller (not shown in FIG.
1
), and the system processor whenever a DMA data transfer starts or stops. That is, ownership of the system memory
200
may pass from the system processor to the IO device
10
, or from the IO device
10
to the system processor.
Moreover, a copy of the information stored in the system memory
200
may also be stored in a system processor memory cache
400
to let the system processor access the information more quickly. If so, the information stored in, or the “state” of, the system processor memory cache
400
must be consistent with the information stored in, or the “state” of, the system memory
200
when an ownership change between the IO device
10
and system processor takes place. Note that it is only necessary to bring the system processor memory cache
400
into a state consistent with the system memory
200
at these key synchronization points, and not in between the ownership changes.
This management of the system processor memory cache
400
can delay the transfer of information between the IO device
10
and system memory
200
. For example, the system processor memory cache
400
and system memory
200
may typically be brought into agreement before and/or after the transfer of each individual data item within a buffer. The information is then transferred and the system processor memory cache
400
and system memory
200
may again be made to agree before another transfer of information with the IO device
10
is permitted. The delays caused by this “item-by-item” memory cache management can significantly hamper memory timing, especially if large amounts of isochronous data are involved.
The use of large First-Out (FIFO) buffers in the computer system
100
, such as in a DMA controller, may solve this problem by storing isochronous information when the system memory
200
cannot be accessed. In this case, information being transferred between the IO device
10
and the system memory
200
can be stored to, or retrieved from, the buffer when the main memory
200
is not available. This buffering can reduce the delays or gaps in an isochronous stream within the computer system
100
, but may increase the cost, lower the performance and/or make the computer system
100
more difficult to build, validate and test. Moreover, unless these problems are solved the system may still not deliver information to or from the system memory
200
in a reliable and timely fashion.
SUMMARY
In accordance with an embodiment of the present invention, isochronous information is transferred between an IO device and a first buffer (N) of a plurality of buffers in a system memory. The information stored in the plurality of buffers is also subsequently stored in a memory cache. The state of the memory cache for the buffer N is managed substantially simultaneously with a second transfer of isochronous information between the IO device and a second buffer in the system memory.


REFERENCES:
patent: 4298929 (1981-11-01), Capozzi
patent: 5544293 (1996-08-01), Nozawa
patent: 5592628 (1997-01-01), Ueno et al.
patent: 5765186 (1998-06-01), Searby
patent: 6012117 (2000-01-01), Traw et al.

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