Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant
Reexamination Certificate
1998-12-18
2001-06-19
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Diffusing a dopant
C438S365000, C438S563000, C438S564000, C438S368000
Reexamination Certificate
active
06248650
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to improvements in semiconductor processing techniques, and more particularly to improved semiconductor structures and associated methods for making semiconductor structures, or the like, and still more particularly to improvements in a semiconductor structure, and associated method of making, of a semiconductor structure not requiring certain mask and implant steps.
BACKGROUND OF THE INVENTION
In the fabrication of self-aligned, double polysilicon (sometimes referred to herein as “poly”) bipolar junction transistor (hereinafter “BJT”) structures, the polysilicon from which the base-conductor is formed is typically doped with boron by ion implantation. The connection between the extrinsic base and the intrinsic base region is formed by a lateral diffusion of this boron from the base conductor into the underlying silicon. The conductor for contact to the extrinsic base is formed by the base polysilicon. In order to achieve a very low resistance base connection and contact, the polysilicon must be very heavily doped. Boron doses on the order of 5×10
15
cm
2
to 1×10
l6
cm
2
are typically used.
Since the base polysilicon must be kept relatively thin in order to reduce vertical base contact resistance and to create low emitter contact structure aspect ratios, and since the boron implant must be completely contained within the base polysilicon layer to provide a repeatable link-up diffusion and shallow extrinsic base junction, the energy of the boron implant must be kept relatively low. This means that a relatively costly implant step is required. The implant step is costly due to the low throughput that results from low energy boron implants at the required high dosage concentrations.
In a double poly self aligned bipolar junction transistor (DPSA BJT) in a BiCMOS implementation, a single polysilicon is typically used for both the gate of MOS devices and the base polysilicon in the BJT. As a result, separate patterning and implant steps are used to dope the base polysilicon and the gate poly for these devices. A representative section view of a prior art BJT is shown in FIG.
1
.
What is needed is a method for eliminating the need for separate patterning and implant steps in a BiCMOS process in the formation of the base polysilicon of the BJT and the gate of the MOS device.
It is with the foregoing problems in mind that the instant invention was developed.
SUMMARY OF THE INVENTION
The present invention concerns an emitter contact structure for, and associated method for making, a bipolar junction transistor in a BiCMOS device. In accordance with a broad aspect of the invention, it has been discovered that by using a boro-silicate-glass inter-poly-dielectric (BSG IPD) between the base and emitter polysilicon in a bipolar or BiCMOS fabrication, the costly extrinsic base mask and implant can be avoided.
The instant invention encompasses a bipolar transistor including a collector region, an intrinsic base region within the collector region, an extrinsic base region within the collector region, and a base link-up region within the collector region between the intrinsic base region and the extrinsic base region. An emitter region is positioned within the intrinsic base region. A base electrode overlays and is in electrical communication with a portion of the extrinsic base region and the base link-up region, and a doped inter-polysilicon dielectric layer overlays a portion of the base electrode. A capping layer is positioned above the inter-polysilicon dielectric layer, and an emitter electrode overlays the inter-polysilicon dielectric layer and the emitter region.
The doped inter-polysilicon dielectric layer can be BSG or PSG, depending on the application, and for instance preferably 5% Boron or PSG by weight. The doped inter-polysilicon dielectric layer overlaps at least a portion or the extrinsic base and the inner end of the base electrode. The doped inter-polysilicon dielectric layer supplies dopant to form the extrinsic base region and the base link-up region.
The instant invention also encompasses a method for constructing a bipolar transistor in a bipolar process, which includes the acts of providing a semiconductor substrate having a collector region, forming a gate electrode layer on the collector region, and forming an inter-polysilicon dielectric layer, having a first dopant, on the polysilicon layer. A capping layer is formed on the inter-polysilicon dielectric layer, and a window is formed through the capping layer, inter-polysilicon dielectric layer, and base electrode layer to a top surface of the substrate. The intrinsic base region is formed in the collector region, and an emitter electrode layer is formed, having a second dopant, on the capping layer and extends into the window to contact the intrinsic base region. The first dopant is diffused from the inter-polysilicon dielectric layer into the collector region, through the base electrode, to form an extrinsic base region and a base link-up region. The second dopant is diffused from the emitter polysilicon layer into the intrinsic base region to form an emitter region therein. The emitter electrode is then patterned with photoresist to selectively cover the emitter electrode over the window, and the emitter electrode layer, the capping layer, and the inter-polysilicon layer are etched to remove the layers from the base electrode where not covered with photoresist.
The acts of forming the first dopant and forming the second dopant can be combined in a rapid thermal anneal step.
Further, the instant invention encompasses a method for constructing a bipolar transistor in a BiCMOS process, including the acts of providing a semiconductor substrate having a collector region, forming a gate electrode layer on the collector region, forming an inter-polysilicon dielectric layer, having a first dopant, on the polysilicon layer, and forming a capping layer on the inter-polysilicon dielectric layer. A window is formed through the capping layer, inter-polysilicon dielectric layer, and base electrode layers to open on a top surface of the substrate. The intrinsic base region is formed in the collector region. An emitter electrode layer, having a second dopant, is formed on the capping layer and extends into the window to contact the intrinsic base region. The emitter electrode is patterned with photoresist to selectively cover the emitter electrode over the window. Then the emitter electrode layer, the capping layer, and the inter-polysilicon layer, are etched where not covered with photoresist to remove the layers from the base electrode. The first dopant from the inter-polysilicon dielectric layer is diffused into and through the base electrode, to dope the base electrode with the first dopant, and to form an extrinsic base region and a base link-up region in the collector region. The second dopant is then diffused from the emitter polysilicon layer into the intrinsic base region to form an emitter region therein
A silicide layer can then be formed on the base electrode to improve the resistivity characteristics of the base electrode, if desired.
The instant invention further encompasses a method for constructing a bipolar transistor in a BICMOS process, comprising the acts providing a semiconductor substrate having a collector region, forming a gate electrode layer on the collector region, forming an inter-polysilicon dielectric layer, having a first dopant, on the polysilicon layer, and forming a capping layer on the inter-polysilicon dielectric layer. A window is formed through the capping layer, inter-polysilicon dielectric layer, and base electrode layer to open on a top surface of the collector region in the substrate. The intrinsic base region is formed in the collector region, and an emitter electrode layer, having a second dopant, is formed on the capping layer and extends into the window to contact the intrinsic base region. The emitter electrode is then patterned with photoresist to selectively cover the emitter electrode over the window. The emitter electr
Bowers Charles
Brady III W. James
Garner Jacqueline J.
Huynh Yennhu B.
Telecky , Jr. Frederick J.
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