Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-23
2001-01-30
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000, C257S355000
Reexamination Certificate
active
06180984
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to integrated circuit impedance devices. There are typically a limited number of device types that are used in making most integrated circuits. The most common devices are the N-channel and P-channel transistors. Most logical functions can be implemented using a combination of only these two devices. However, some applications may require additional device types.
In one application, for example, resistors may be incorporated into a data storage circuit to increase the Single Event Upset (SEU) hardness of the data storage circuit. The resistors are typically connected in a cross-coupled configuration, as shown in FIG.
1
. The cross-coupled resistors increase the SEU hardness of the data storage circuit by increasing the feedback delay around the data storage circuit. The increased delay provides the data storage circuit more time to remove any charge that is deposited during a radiation event. A further discussion of the use of resistors to increase the SEU hardness of a data storage circuit can be found in co-pending U.S. patent application Ser. No. 09/219,807, filed Dec. 23, 1998, entitled “SEU Hardening Circuit”, which is incorporated herein by reference.
For many integrated circuit processes, such as MOSFET type process, the resistors are formed using a single polysilicon layer. The polysilicon layer is often the same polysilicon layer that is used to form the gates of the N-channel and P-channel transistors. The polysilicon layer of the N-channel and P-channel transistors is usually covered with a silicide layer to further enhance the conductivity thereof To make the polysilicon layer more resistive, therefore, a silicide blanking step must typically be performed. The silicide blanking step blanks the silicide layer from those locations that correspond to the polysilicon resistors. Additional processing may also be requires, such as selective implant processing, to achieve the desired resistance values. Because of this additional processing, the cost of producing such integrated circuits may be increased.
In addition, when such polysilicon resistors are used in conjunction with a typical gate array, the achievable gate density of the gate array may be reduced. In a typical gate array, such as a Sea-Of-Gates (SOG) gate array, all of the underlayers are typically prefabricated. The polysilicon and silicide layers are usually part of the pre-fabricated underlayers. To personalize the gate array, one or more metal layers are used to interconnect the pre-fabricated devices.
To make the polysilicon resistors widely available, the resistors are typically distributed among the standard transistors. For most circuits, however, only a small fraction of the gates require a resistor. For example, in a radiation-hard integrated circuit, only selected data storage circuits (e.g. latches, flip-flops, etc.) may need cross-coupled resistors to achieve a desired SEU hardness. The remaining circuits, including much of the combinational logic, typically does not need polysilicon resistors. Therefore, and because the resistors are typically distributed across the gate array, most of the resistors go un-used. These un-used resistors consume valuable silicon real-estate which could otherwise be used for transistors to increase the gate density of the gate array.
Therefore, it would be desirable to provide a device that can serve a dual function as either an impedance (e.g. resistor) or a standard transistor, depending on the metal interconnect layers provided. It would also be desirable if the device did not require any additional processing steps relative to those required for a conventional transistor.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages of the prior art by first providing a device that can serve as either a resistor or a transistor. Preferably, the same underlayers are used to form the resistor and transistor. The resistor may then be formed by selecting a first metal interconnect configuration, and the transistor may be formed by selecting a second metal interconnect configuration. Because of the dual transistor/resistor nature of this device, the density of a typical gate array can be maintained while still providing readily available resistors for special applications such as SEU hardening selected data storage circuits. In addition, and because no special processing is typically required, the device may be desirable in other types of structures such as standard cells and custom logic. The term resistor as used herein is not limited to a conventional linear resistor, but rather may include all impedance producing devices including JFET and other field effect devices that can modulate a resistance.
In one illustrative embodiment, an impedance device is formed using the underlayers of an SOI transistor. The MOSFET SOI transistor has a source, a drain, a body, and a gate. The body of the transistor extends lengthwise under the gate but above the buried oxide from a first end body region on one side of the source/drain to a second end body region on the other side of the source/drain. The first end body region is coupled to a first terminal of the resistor, and the second end body region is coupled to a second terminal of the resistor.
In this configuration, the body region under the gate provides a bulk type resistance. If desired, the resistance can be modulated by controlling the voltage applied to the source, drain, gate and/or back-side of the SOI transistor. This modulation is JFET like in nature. In one embodiment, the source and/or drain are coupled to the first terminal of the resistor, and the gate is coupled to a predetermined voltage such as VDD or VSS. In other embodiments the source and/or drain may be left floating, or connected to VDD (n-channel MOSFET) or VSS (p-channel MOSFET). The gate may be coupled to VDD or VSS, or may be coupled to the first or second terminal of the resistor. Preferably, the resistor may be formed using the underlayers of a n-channel SOI transistor or a p-channel SOI transistor.
Rather than using the body of only one transistor, it is contemplated that a resistor may be formed using a body between two adjacent transistors. For example, a first transistor may have a first field region that defines the source and/or drain region of the first transistor. Likewise, a second transistor may have a second field region that defines the source and/or drain region of the second transistor. The resistor may be formed between the first and second field regions by including a body region therebetween. The body may extend lengthwise from a first end body region on one side of the first/second field regions to a second end body region on the other side of the first/second field regions. The first end body region may be coupled to the first terminal of the resistor, and the second end body region may be coupled to the second terminal of the resistor.
In this configuration, a gate may not be provided over an intermediate body region. Nonetheless, the body region provides a bulk resistance. If desired, the resistance of the intermediate body region may be modulated by applying a selected voltage to the first field region and/or second field region. The first field region and/or the second field region may be coupled to the first terminal of the resistor, left floating, or may be tied to a predetermined voltage such as VDD (n-channel MOSFET) or VSS (p-channel MOSFET).
If the SOI technology is fully depleted, rather than only partially depleted, a depletion region typically extends from the gate oxide to the buried oxide when the gate, source, drain, and first and second terminals are at, for example, an equal voltage. This depletion region causes the resistor to be fully pinched off under certain bias conditions. This can be unacceptable in some applications, such as in some SEU hardening circuits where the resistor must allow some leakage current to flow.
Therefore, when using a fully depleted SOI technology, it is cont
Fechner Paul S.
Golke Keith W.
Abraham Fetsum
Fredrick Kris T.
Honeywell Inc.
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