Transistor and logic circuit of thin silicon-on-insulator...

Details Transistor and logic circuit of thin silicon-on-insulator... Transistor and logic circuit of thin silicon-on-insulator...

1999-04-08

2001-08-28

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000, C257S349000, C257S368000, C257S369000, C438S282000, C438S298000, C438S910000, C438S479000, C438S517000

Reexamination Certificate

active

06281550

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to silicon-on-insulator (SOI) integrated circuits, and more particularly, transistor and logic circuits using gate induced drain leakage current formed on a SOI.
BACKGROUND OF THE INVENTION
Silicon-on-insulator (SOI) is gaining popularity as a new technology. Devices formed in SOI have demonstrated significant performance improvement over devices fabricated on bulk wafers. This is because silicon devices have problems with inherent parasitic to junction capacitances. One way to avoid this problem is to fabricate silicon devices on an insulating substrate. Hence, the reason for SOI technology is that it offers the highest performance in terms of power consumption and speed for a given feature size due to minimizing parasitic capacitance.
The present invention provides new transistor and logic circuits that are particularly well suited for SOI wafers.
SUMMARY OF THE INVENTION
A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the V
cc
and V
ss.
The connection of fan-outs (between the output and input) can be implemented by either capacitor coupling or conventional contact and metal line. The transistor structure and operation is useful for high-performance, low-voltage, and low-power VLSI circuits on SOI wafers.


REFERENCES:
patent: 5448513 (1995-09-01), Hu et al.

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