Method of removing polysilicon residual in a LOCOS isolation...

Details Method of removing polysilicon residual in a LOCOS isolation... Method of removing polysilicon residual in a LOCOS isolation...

1999-04-30

2001-06-12

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S444000

Reexamination Certificate

active

06245643

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacturing of integrated circuits, and in particular, to a method of removing polysilicon residual formed during a local oxidation of silicon (LOCOS) isolation process using an etching selectivity solution.
2. Description of the Prior Art
A continuing trend today in the design of integrated circuits (IC's) is to increase circuit density thereby incorporating more circuit devices into a given area of an IC chip. Techniques for increasing device density of an IC include techniques for reducing the size of active areas of devices in the IC, and techniques for reducing the size of isolation areas between adjacent active areas. The goal of such efforts is to reduce the overall size of the IC's without compromising performance.
FIG. 1A
illustrates a cross-sectional view of a portion of an IC
10
as manufactured in accordance with a typical prior art local oxidation of silicon (LOCOS) based method. Devices, or components, of the IC
10
are typically formed using a substrate
12
. A first step in semiconductor manufacturing is the division of the substrate
12
into: an active area
14
in which thin-film layers are formed on and above substrate
12
to create active devices of the IC; and a field oxide region
16
providing isolation between adjacent ones of the active areas. The layers formed in the active area
14
typically include: a pad oxide layer
18
(e.g., SiO
2
) formed on and above substrate
12
; a silicon nitride (Si
3
N
4
) layer
20
formed on and above pad oxide layer
18
for masking purposes as further explained below; and ion implanted, or doped regions (not shown) formed within substrate
12
.
FIG. 1B
illustrates a detailed view of a typical transition region, or bird's beak,
22
formed in the field oxide region
16
at an interface between the active area
14
and the field oxide region
16
as a result of a typical prior art LOCOS based prior art method of forming the field oxide region. The field oxide region
22
is referred to as a “birds beak” because it is characterized by a graduated increase in thickness as it extends in a direction from the pad oxide layer
18
to the field oxide region
16
. If a field oxide region is formed to have a long bird's beak
22
, then the bird's beak
22
of the field oxide region extends under the masking silicon nitride layer
20
, thereby encroaching upon otherwise usable portions of the active area
14
. Also, the bird's beak creates stress and defects in the silicon in the active areas.
In order to increase the density of the IC, it is desirable to reduce the length of the bird's beak
22
. However, reducing the length of bird's beak
22
may compromise IC performance characteristics. For example, decreasing the length of bird's beak
22
may degrade the isolation effect provided by field oxide region
16
, thereby causing a leakage current. Thus, there is a design tradeoff between the length of bird's beak
22
and IC performance characteristics. Several prior art techniques have been developed for minimizing the length of the bird's beak without significantly compromising IC performance characteristics. For example, U.S. Pat. No. 5,393,692, (entitled “Recessed Side-Wall Poly Plugged Local Oxidation”, invented by Wu, and assigned to Taiwan Semiconconductor Manufacturing Company) discloses a method of forming a field oxide isolation region with reduced bird's beak length.
FIGS. 2A-2D
illustrate cross-sectional views of an IC
50
at sequential steps of a prior art LOCOS based method of forming a field oxide isolation region having reduced bird's beak encroachment into active areas. Referring to
FIG. 2A
, initial steps of the prior art method include: forming a first pad oxide layer
54
of silicon dioxide (SiO
2
) on and over a substrate
52
; forming a silicon nitride (Si
3
N
4
) layer
56
on and over the first pad oxide layer
54
for the purpose of masking; and performing photolithography and isotropic (wet) etching, as illustrated by lines
58
, in order to selectively remove portions of the silicon nitride layer, first pad oxide layer, thereby exposing a portion of the top surface of the substrate
52
. As a result of these steps, active regions
60
are defined. Because of the characteristics of isotropic etching, which typically include an undercutting effect, a cavity
62
is formed below each of the silicon nitride layers
56
adjacent to the field oxide region.
Referring to
FIG. 2B
, a second pad oxide layer
64
of silicon dioxide is grown on and over the exposed portion of substrate
52
. Subsequently, polysilicon material is deposited over the substrate
52
, and an etch back step is performed to form a polysilicon spacer
66
adjacent to the silicon nitride layer in the active regions
60
. A polysilicon plug is formed in the cavity
62
(
FIG. 2A
) underlying the silicon nitride layer
56
. As explained below, the polysilicon spacer
66
, which is used to form the field oxide region, provided for reducing the length of the bird's beak
22
(FIG.
1
B). Also, the polysilicon plug formed in the cavity
62
along the edges of the active region
60
is intentionally formed to inhibit encroachment of the bird's beak
22
(
FIG. 1B
) into the active region
14
.
Referring to
FIG. 2C
, the prior art method of forming a field oxide further includes performing a LOCOS based process of oxidizing the substrate
52
to form a field oxide layer
68
by subjecting the substrate
52
to a high temperature and oxygen rich environment causing rapid oxidation. During the field oxidation process, the polysilicon spacer
66
and polysilicon plug formed in the cavity
62
provide barrier structures in order to achieve reduction of bird's beak encroachment. The polysilicon spacer
66
is substantially consumed. However, the polysilicon plug in the cavity
62
(FIG.
2
A), is at least partially protected from exposure during the LOCOS based oxidation process by the silicon nitride layer
56
. As a result, the polysilicon plug in the cavity
62
is not completely oxidized, and a polysilicon residual
70
of the polysilicon plug remains in the cavity
62
.
Referring to
FIG. 2D
, the silicon nitride layer
56
and the pad oxide layer
54
of the active region
60
are removed by wet etching. A problem arises in this procedure because the polysilicon residual
70
may not be dissolved by a conventional etch solution, such as hydrofloride (HF), and therefore polysilicon residual material remains in the etch solution and flows into a solution tank (not shown). The resulting problem is that after completion of the wet etching process, the polysilicon residual material remaining in the etching solution can cause contamination of the IC
50
during subsequent processing steps. It is therefore necessary in the prior art process to change the etching solution and clean the tank after the step of wet etching the silicon nitride layer
56
and the pad oxide layer
54
of the active region
60
.
Thus, there is a need for a method of removing polysilicon residual of a polysilicon plug used in limiting encroachment of a bird's beak of a field oxide isolation region, wherein etching solution needed for subsequent process steps is not contaminated by the polysilicon residual.
SUMMARY OF THE INVENTION
Briefly, a presently preferred embodiment of the present invention provides an improved method of forming a field oxide isolation region in a semiconductor device. The method includes an advantageous selective etching sub-process for efficiently removing polysilicon residual of a polysilicon plug which is used in limiting encroachment of the “bird's beak” of the field oxide isolation region into an active region.
The method of forming a field oxide isolation region includes the steps of: forming a first pad oxide layer over a semiconductor substrate; forming a silicon nitride layer over the first pad oxide layer; patterning and etching the silicon nitrid

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