Method of self programmed built in self test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Reexamination Certificate

active

06230290

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits and, more particularly, to, for example, Dynamic Random Access Memories (DRAMs) with Built In Self Test (BIST) Capability.
2. Background Description
FIG. 1
is a block diagram of a typical page mode Dynamic Random Access Memory (DRAM) chip with Built In Self Test (BIST) capability. The chip includes a DRAM
100
and a conventional BIST engine
200
that tests the DRAM
100
according to commands defined in a Microprogram ROM
300
.
The test program for this prior art BIST engine
200
may be varied only by changing microcode that is fixed permanently in the microprogram ROM
300
. All test conditions and test sequences are unalterably stored in the microprogram ROM
300
. Thus, regardless of BIST results, the entire microprogram must be executed. Even if more rigorous tests might be desired, they cannot be added without reprogramming the microprogram ROM
300
.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to reduce memory (e.g., DRAM) test time.
It is another object of the present invention to improve the information available from memory (e.g., DRAM) self tests.
The present invention includes a memory (e.g., a Dynamic Random Access Memory (DRAM)) with a self-programmable Built In Self Test (BIST). The memory, which may be a memory (e.g., DRAM) chip, includes a memory core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. The memory may also include current and temperature monitors to monitor current and temperature during test. Initially, the BIST engine tests the memory normally with preselected tests. However, after initial testing, subsequent tests are varied based on test history. So, the Self-Program Circuit may proceed with the self test at more or less stringent conditions.


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Toshio Takeshima, et al, “A 55-NS 16-MB DRAM with Built-in Self-Test Function Using Microprogram ROM”, IEEE Journal of Solid-State Circuits, vol. 25, No. 4, Aug. 1990, pp. 903-911.

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