Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1997-08-18
2001-04-03
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S720000, C438S902000
Reexamination Certificate
active
06211078
ABSTRACT:
FIELD
The present invention relates to the use of resist for patterning conductive layers in semiconductor processing. More particularly, the present invention relates to improved adhesion of resist to a titanium nitride layer for use in patterning a layer underlying the titanium nitride layer.
BACKGROUND OF THE INVENTION
In the fabrication of a semiconductor integrated circuit (IC), material is deposited, or otherwise formed, in layers. Some of these layers are then patterned to form the individual devices within the IC. Layers of conductive material (e.g., metal, such as aluminum) formed over the individual devices are patterned to form metal lines. The metal lines provide connections with respect to the individual devices of the IC.
Generally, a conductive layer to be patterned is supported by a substrate during processing. During patterning, a photoresist layer is formed over the conductive layer to be patterned. The photoresist layer is then exposed to ultraviolet radiation as part of a photolithographic process used to perform the patterning. The photoresist layer is exposed such that a desired pattern is imparted to the photoresist layer after its selective removal. The photoresist is patterned to define features having critical dimensions in underlying layers. To remove portions of the photoresist layer (exposed or unexposed, depending on the type of photoresist used), a developer solution is used. The underlying conductive layer to be patterned is, thus, exposed in regions where the photoresist was removed using the developer solution. An etchant is then typically used to remove the underlying conductive layer, resulting in a patterned conductive layer supported by the substrate.
At the interconnect level in the fabrication process, a significantly rough surface topography typically exists due to the numerous patterned layers thereunder. This rough surface topography causes an uneven level of reflection from the conductive layer into the overlying photoresist layer when the photoresist is exposed to ultraviolet radiation. The uneven level of reflection results in poor definition of the pattern in the photoresist layer. Thus, conventionally, to control the amount of reflection from underlying layers, titanium nitride (TiN) is conventionally formed between the underlying layer and the photoresist layer to act as an antireflective layer.
As device density is increasing to meet consumer demands for faster processing of data, the amount of interconnect required between devices is also increasing. To accommodate this increase in the amount of interconnects needed per chip, the pitch (i.e., width) of metal lines and spaces therebetween is being decreased and the interconnects are being formed in an increasing number of layers within the IC. As the pitch tightens, such as, for example, about 0.6 microns and below, adhesion of photoresist to the underlying TiN layer is problematic. As a result of poor photoresist adhesion to the TiN layer, patterning of the underlying conductive layer is also poor, particularly at the interface between the photoresist and the underlying layer. Therefore, there is a need for methods to improve resist adhesion on a TiN layer for use in patterning of underlying conductive layers.
SUMMARY OF THE INVENTION
A method for use in patterning a conductive layer of an integrated circuit in accordance with the present invention includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. The titanium nitride layer is oxidized resulting in an oxide region. The oxide region has a thickness in the range of about 5 nanometers to about 30 nanometers. A photoresist layer is formed on the oxide region.
In various embodiments of the method, the oxide region has a thickness in the range of about 5 nanometers to about 20 nanometers, the oxidation of the titanium nitride layer includes oxidizing the titanium nitride layer at a temperature less than about 400° C., and/or the oxidation the titanium nitride layer includes oxidizing the titanium nitride layer at a pressure in the range of about 10 atmospheres to about 50 atmospheres.
In further embodiments of the method, the oxidation of the titanium nitride layer includes oxidizing the titanium nitride layer using ozone, subjecting the titanium nitride layer to a solution for reaction with the titanium nitride layer, or subjecting the titanium nitride layer to an oxygen ash. Yet further, the photoresist is a non-chemically amplified photoresist.
In a further method for use in patterning a conductive layer of an integrated circuit in accordance with the present invention, the method includes providing a conductive layer to be patterned and then forming a titanium nitride layer on the conductive layer. An oxide layer is then formed on the titanium nitride layer with the oxide layer having a thickness in the range of about 5 nanometers to about 30 nanometers. A photoresist layer is formed on the oxide layer.
In one embodiment of the method, the forming of an oxide layer includes depositing an oxide layer, preferably a silicon dioxide layer. In a further embodiment, the oxide layer has a thickness in the range of about 5 nanometers to about 20 nanometers.
In various embodiments of the present invention, the method includes patterning the conductive layer to a pitch of less than or equal to about 0.6 microns. In other embodiments of the invention, the titanium nitride layer formed on the conductive layer has a thickness of less than about 600 Å.
Further, in accordance with the present invention, an intermediate structure formed during a semiconductor wafer fabrication process is provided. The structure includes a conductive layer on a substrate, a titanium nitride layer on the conductive layer, an oxide region having a thickness in the range of about 5 nanometers to about 30 nanometers on the titanium nitride layer, and a photoresist layer on the oxide region.
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Everhart Caridad
Micro)n Technology, Inc.
Mueting Raasch & Gebhardt, P.A.
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