Method of manufacturing self-aligned contact

Details Method of manufacturing self-aligned contact Method of manufacturing self-aligned contact

1998-10-01

2001-01-09

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S645000, C438S648000

Reexamination Certificate

active

06171954

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87109378, filed Jun. 12, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a MOS transistor device. More particularly, the present invention relates to a method of manufacturing a self-aligned contact (SAC).
2. Description of Related Art
The conventional method of manufacturing a self-aligned contact includes the steps of forming spacers on the sidewalls of a polysilicon gate structure, wherein the spacer is an insulating layer such as a silicon oxide layer. Then, a second insulating layer is formed over the gate structure, and subsequently the second insulating layer is etched to form a self-aligned contact. The spacers protect the gate structure against any damage during the etching operation. Finally, conductive material, for example, polysilicon or tungsten, is deposited into the contact to form a conductive layer, and then metal silicide is deposited to lower the resistance of the conductive layer further.
FIGS. 1A through 1E
are cross-sectional views showing the progression of manufacturing steps in producing a self-aligned contact according to a conventional method.
First, as shown in
FIG. 1A
, a substrate
100
is provided. The substrate
100
can be a lightly doped P-well or a P-type semiconductor, for example. Next, a gate structure
102
is formed over the substrate
100
. The gate structure
102
is formed by first depositing a gate oxide layer
104
over the substrate
100
, and then forming a conductive stack layer
106
over the gate oxide layer
104
. The conductive stack layer
106
is formed by first depositing a doped polysilicon layer (not shown) over the gate oxide layer
104
, and then forming a metal silicide layer (not shown) over the doped polysilicon layer. For example, the gate oxide layer
104
can be formed by heating the substrate
100
to a temperature of about 800-1000° C. in an oxygen-filled atmosphere. The doped polysilicon layer of the conductive stack layer
106
can be formed by a deposition process using a low-pressure chemical vapor deposition (LPCVD) method. In general, impurities for the doped polysilicon layer including arsenic or phosphorus are deposited concurrently with the polysilicon deposition. Alternatively, the impurities can be implanted after a polysilicon layer is formed. The metal silicide layer of the conductive stack layer
106
, for example, can be tungsten silicide, titanium silicide or molybdenum silicide. After the gate structure
102
is formed, an ion implantation operation is carried out to form a lightly doped source/drain region
110
. For example, using the gate structure
102
as a mask, N-type ions such as arsenic or phosphorus are implanted into the substrate
100
.
Next, as shown in
FIG. 1B
, an insulating layer
114
is formed over the substrate
100
using, for example, a chemical vapor deposition (CVD) method. The insulating layer
114
can be a silicon oxide layer or a silicon nitride layer, for example.
Thereafter, as shown in
FIG. 1C
, the insulating layer
114
is anisotropically etched back to form spacers
114
a
on the sidewalls of the gate structure
102
. Consequently, a portion of the lightly doped source/drain region
110
is exposed and a self-aligned contact opening
122
is formed above the source/drain region
110
. The spacers
114
a
not only protect the gate structure
102
against damage in etching operations, but also serve as a mask in the formation of heavily doped source/drain regions. In the subsequent step, using the spacers
114
a
as a mask, another ion implantation is carried out using a high dosage of N-type or arsenic ions, thereby forming a heavily doped source/drain region. Hence, source/drain regions
116
having A lightly doped drain (LDD) structure are formed.
Next, as shown in
FIG. 1D
, a dielectric layer
118
is formed over the substrate
100
. For example, using a mixture of silane and oxygen as a reactive gas, a chemical vapor deposition (CVD) method is used to form a silicon oxide layer. Subsequently, the dielectric layer
118
is planarized using, for example, a chemical-mechanical polishing (CMP) method. Thereafter, photolithographic and etching techniques are used to pattern the dielectric layer
118
, forming a self-aligned contact opening
122
that exposes the heavily doped source/drain region
116
.
However, to avoid misalignment of the self-aligned contact (SAC) opening
122
that might possibly lead to short-circuiting of subsequently formed SAC with the gate structure
102
, the width of the SAC opening
122
must be smaller than the distance between two neighboring gate structures
102
. Since no etching stop layer is formed between the gate structure
102
and the dielectric layer above, the gate structure
102
may be damaged when the dielectric layer
118
is etched to form the SAC opening if misalignment occurs. In particular, as line width of devices continues to shrink, any misalignment can easily lead to a considerable increase in contact resistance between the contact and the source/drain region. In fact, design rules have set the lower limit of line width to about 0.25 &mgr;m because line width smaller than that will cause too much resistance in the self-aligned contact.
Next, as shown in
FIG. 1E
, conductive material such as tungsten is deposited over the dielectric layer
118
using, for example, a chemical vapor deposition (CVD) method. The conductive material completely fills the self-aligned contact opening
122
. Thereafter, an etching back method or a chemical-mechanical polishing (CMP) method is used to remove a portion of the conductive layer and expose the dielectric layer. Consequently, a self-aligned contact
124
is formed inside the self-aligned contact opening
122
.
However, the aforementioned self-aligned contact will misalign when the self-aligned contact opening is formed. Misalignment of the self-aligned contact can easily lead to undesirable electrical connection between the SAC and its neighboring gate structure. Therefore, width of the SAC must be smaller than the distance between two neighboring gate structures. Because there is no way of increasing width of a self-aligned contact opening in an era when line width of semiconductor devices continues to decrease, contact resistance between the source/drain region and the self-aligned contact will continue to rise.
In light of the foregoing, there is a need to improve the method of forming a self-aligned contact.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of forming a self-aligned contact. This method includes forming a cap layer over the gate structure so that the cap layer acts as an etching stop layer when the conductive layer is etched. The method also includes forming a polysilicon layer over the substrate so that the source/drain region is electrically coupled to the source/drain region, wherein the polysilicon layer also serves as an etching stop layer when another conductive layer is etched. Therefore, besides forming a self-aligned contact, the method is also capable of providing a self-aligned contact opening that has a width greater than the distance between two neighboring gate structures. Hence, contact resistance existing between the source/drain region and the self-aligned contact can still be maintained despite a reduction of the line width.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a self-aligned contact. The method comprises the steps of forming a cap layer on top of a gate structure, and then concurrently forming sidewall spacers on each side of the gate structure and a self-aligned contact opening above the source/drain region. Next, a polysilicon plug that couples electrically with the source/drain region is formed inside the self-aligned c

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