Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Utility Patent
1998-10-27
2001-01-02
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S357000, C361S090000
Utility Patent
active
06169311
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit, and more particularly to, a semiconductor integrated circuit composed to protect an input buffer from breakage caused by static discharge.
BACKGROUND OF THE INVENTION
In assembling a semiconductor device into a semiconductor package or transporting it, part of internal element of the semiconductor device may be deteriorated or broken by static discharge. To protect an integrated circuit from such damage, a semi-custom integrated circuit such as a gate array and a standard cell is often composed combining several common transistors in advance provided with input and output circuits including a static electricity protection function, without discriminating between input pad and output pad to facilitate the formation of LSI designing library.
A conventional CMOS (complementary metal-oxide semiconductor) type input and output circuit is, for example as shown in
FIG.1
, composed by, in advance, providing p-channel transistors
3
,
4
,
5
and
6
with same gate length and gate width and n-channel transistors
7
,
8
,
9
and
10
with same gate length and gate.
In an input circuit section
15
, the p-channel transistors
3
,
4
are connected between a power source line
16
and an input pad
1
and the n-channel transistors
7
,
8
are connected between a ground line
17
and the input pad
1
. The gate electrodes of the p-channel transistors
3
,
4
are connected to the power source line
16
, and the gate electrodes of the n-channel transistors
7
,
8
are connected to the ground line
17
.
The p-channel transistor
3
and the n-channel transistor
7
compose an input protective circuit
50
, and the p-channel transistor
4
and the n-channel transistor
8
compose an input protective circuit
19
.
Also, in an output circuit section
23
, thep-channel transistors
5
,
6
are connected between the power source line
16
and the output pad
2
and the n-channel transistors
9
,
10
are connected between the ground line
17
and the output pad
2
. The gate electrodes of the p-channel transistor
5
and the n-channel transistor
9
are connected to an internal circuit
20
. The p-channel transistor
5
and the n-channel transistor
9
compose an output circuit
52
.
The p-channel transistor
6
and the n-channel transistor
10
, which do not contribute to the signal outputting from the internal circuit
20
, compose an output protective circuit
53
, like the input protective circuit.
With the above composition, the input and output circuit including the static electricity protection function can be efficiently realized.
In recent years, semiconductor integrated circuits have been increasingly provided with large capacity. Along with this, the operation speed has been enhanced. However, when the parasitic resistance of diffusion layer is reduced by silicidation or salicidation, where the diffusion layer for source electrode and drain electrode of transistor is covered with high-melting-point metal, to enhance the operation speed, static electricity stress may influence more directly the diffusion layer than ever. In particular, the drain part of the n-channel transistor is likely to be damaged.
To solve this, for example as shown in
FIG. 2
, a simple solution where resistance elements
11
,
12
,
13
and
14
are uniformly inserted to the drain parts of the n-channel transistors
7
,
8
,
9
and
10
can be easily imagined.
However, concerning the input circuit section
15
, the placement of the resistance elements
11
,
12
restricts current flow to the n-channel transistors
7
,
8
thereby preventing the n-channel transistors
7
,
8
from breaking down, the gate oxide film in the internal circuit
20
may be damaged before the protective circuit operates because the input pad
1
is directly connected to the gate electrodes of a p-channel transistor
21
and a n-channel transistor
22
inside the internal circuit
20
.
A conventional technique to solve this problem is, for example, disclosed in Japanese patent application laid-open No. 9-97844 (1997), regarding an input protective circuit. As shown in
FIG. 3
, in the conventional input protective circuit
54
, the p-channel transistor
3
is connected between the power source line
16
and the input pad
1
, and the n-channel transistor
7
is connected between the ground line
17
and the input pad
1
. The gate electrode of the p-channel transistor
3
is connected to the power source line
16
, and the gate electrode of the n-channel transistor
7
is connected to the ground line
17
. The n-well resistance
11
is inserted between the input pad
1
and the internal circuit
20
.
Also, as another conventional technique, for example, Japanese patent application laid-open No. 9-97844 (1997) discloses an output protective circuit. As shown in
FIG.4
, in the conventional output protective circuit
55
, the p-channel transistor
6
and the n-channel transistor
10
are connected in series, the source electrode of the p-channel transistor
6
is connected to the power source line
16
, and the source electrode of the n-channel transistor
10
is connected to the ground line
17
. The gate electrode of the p-channel transistor
6
is connected to the power source line
16
, and the gate electrode of the n-channel transistor
10
is connected to the ground line
17
. Further, the resistance element
13
is inserted between the input pad
2
and the connecting part of the p-channel transistor
6
and the n-channel transistor
10
. The output protective circuit
55
is connected in parallel to the output circuit
24
.
By the input protective circuit
54
in
FIG. 3
, the input protection in the internal circuit
20
can be surely performed. However, in the circuit composition in
FIG.3
, the n-channel transistor
7
itself cannot be prevented from breaking down because the n-channel transistor
7
as the protective element is, as mentioned earlier, directly connected to the input pad
1
.
Also, if the circuit composition of the input protective circuit
54
is unalteredly applied to the output circuit as well, in particular, when outputting High level in a high drive output buffer, the resistivity of the n-well resistance element
11
becomes unnegligible and the output drive performance must be significantly deteriorated because the elemental performance of p-channel transistor is generally lower than that of n-channel transistor. When solving this, the layout area of the output p-channel transistor must be enlarged and therefore a circuit composition available for both the input circuit and the output circuit cannot be realized. Thus, it cannot be unalteredly applied to a gate array or a standard cell.
By the output protective circuit
55
in
FIG.4
, the static electricity protection of the output circuit can be performed without deteriorating the drive performance of the output circuit. However, in the circuit composition in
FIG. 4
, the n-channel transistor
9
itself cannot be prevented from breaking down because the n-channel transistor
9
is, as mentioned earlier, directly connected to the output pad
2
. In particular, when the resistance element
13
is relatively large, the n-channel transistor
9
may become more likely to be broken down. It is very difficult to choose an optimum resistance value. Also, two kinds of circuit compositions, the output circuit
24
and the output protective circuit
55
, have to be provided for one pad. Therefore, it is not multipurpose and cannot be unalteredly applied to a gate array or a standard cell.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a semiconductor integrated circuit that can prevent the input buffer from breaking down by static discharge and can be easily applied to a semi-custom integrated circuit, such as a gate array and a standard cell.
According to the invention, a MOS-type semiconductor integrated circuit, comprises:
an input circuit section including an n-channel transistor, a p-channel transistor and a protective resistance connect
Hardy David
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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