Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-08
2001-07-10
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C438S151000, C438S225000, C438S694000
Reexamination Certificate
active
06259143
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device of NOR type mask ROM, and more particularly to a semiconductor memory device realizing high speed access and high degree of integration, and a method of manufacturing the same.
2. Related art
FIG. 1
is a plan view showing an example of wiring pattern of a general flat NOR type mask ROM. That is,
FIG. 1
is a plan view of a general cell layout of NOR type mask ROM having embedded digit lines. In a semiconductor substrate
1
, a plurality of embedded digit lines
4
are arranged in stripes alternately with active regions
2
. On the surface of the semiconductor substrate
1
, moreover, a plurality of word lines
6
are arranged in stripes so as to cross perpendicularly with the embedded digit lines
4
. The intersecting region of the active region
2
between the embedded digit lines
4
and the word lines
6
, that is, the region enclosed by double dot chain lines in
FIG. 1
corresponds to a unit memory cell MC. Herein, L refers to the channel length, and the W is the channel width. In this NOR type mask ROM, by implanting impurity ions of the same conductive type as the semiconductor substrate
1
selectively in the region of memory cell MC, the threshold value of the transistor of the memory cell MC can be changed, so that the data can be written in.
A conventional manufacturing method of the NOR type mask ROM shown in
FIG. 1
will be explained below by referring to
FIGS. 2A
to
2
D.
FIGS. 2A
to
2
D are sectional views along line A—A in FIG.
1
. First, as shown in
FIG. 2A
, an oxide film
303
is formed on a P type silicon substrate
301
(semiconductor substrate
1
in FIG.
1
), and a photoresist film
307
is formed thereon, and further the photoresist film
307
is selectively removed from the region which becomes an embedded digit line
304
(digit line
4
) in a later process, that is, the region sandwiching the active region
302
, so that openings
307
a
are formed in stripes at specified intervals in the photoresist film
307
.
Next, as shown in
FIG. 2B
, using the photo resist film
307
as mask, for example, arsenic is implanted as N type impurity in the P type silicon substrate
301
, and embedded digit lines
304
are formed.
Then, after removing the photo resist film
307
and oxide film
303
consecutively, as shown in
FIG. 2C
, the surface of the P type silicon substrate
301
is oxidized, and a gate oxide film
305
made of silicon oxide film is formed on the surface of the P type silicon substrate
301
.
Consequently, as shown in
FIG. 2D
, a polycrystalline silicon film is formed on the entire surface, and later, although not shown, the polycrystalline silicon film is selectively removed by the selective etching technology using the photo resist film, and stripes of word lines
306
(word lines
6
in
FIG. 1
) are formed perpendicular to the embedded digit lines
304
.
In such conventional NOR type mask ROM, in order to enhancing the reading speed of data in the unit memory cells, it is preferred to lower the layer resistance of the embedded digit lines
304
. For this purpose, it is essential to implant the N type impurity for forming the embedded digit lines
305
at high density. However, when the embedded digit line
304
is high in concentration, the junction capacity between the embedded digit line
304
and P type silicon substrate
301
increases, and the propagation speed in the embedded digit line
304
is lowered by the junction capacity. At the same time, the parasitic capacity between the embedded digit line
304
and word line
306
increases, and the propagation speed in the word line
306
is lowered.
To solve such problems, it has been proposed in Japanese Patent Application Laid-Open (JP-A) No. 5-259410 to form a groove at a region where an embedded digit line should be formed in the semiconductor substrate, embed the grooves with insulating region, and form impurity layers at the bottom and side wall of the groove to use as embedded digit lines. In this technique, since the embedded digit lines are formed in the bottom and side wall of the grooves, the parasitic capacity between the embedded digit line and word line can be reduced, and lowering of propagation speed in the word line can be prevented. It is, however, difficult to solve the contradictory problems of the lowering of resistance value of the embedded digit line and the lowering of the junction capacity between the embedded digit line and the semiconductor substrate. Yet, in such constituent of embedding the insulating region in the groove, the occupied area of the unit memory cell increases, which is a problem for realizing a high degree of integration.
SUMMARY OF THE INVENTION
It is hence an object of the present invention to provide a semiconductor memory device including a NOR type mask ROM realizing low resistance of embedded digit lines and reduction of junction capacity in the embedded digit lines simultaneously, capable of reading out from the memory cell at high speed, and realizing a high degree of integration, and a method of manufacturing the same.
A semiconductor memory device of NOR type mask ROM according to the present invention comprises: a semiconductor substrate of one conductive type; an active region formed on the surface of said semiconductor substrate; embedded digit lines arranged in stripes at positions sandwiching said active region; a gate insulating film formed on the surface of said semiconductor substrate; word lines formed in stripes extended in a direction perpendicular to said embedded digit lines on said gate insulating film; and a diffusion layer of other conductive type formed by diffusion of the impurity contained in said semiconductor layer through the side surface of said first groove in said active region. Each of said embedded digit lines are composed of a first groove provided in the surface side region of said semiconductor substrate, a second groove provided at the substrate lower side of said first groove, an insulating film provided on an inner surface of said second groove, and a semiconductor layer doped with impurity of other conductive type embedded in said first groove and second groove.
A manufacturing method of a semiconductor memory device according to the present invention comprises the steps of: forming a first groove in stripe in a region where an embedded digit line should be formed on the surface of a semiconductor substrate; forming a side wall on an inner surface of said first groove; forming a second groove at the lower side of said first groove by using said side wall as a mask; forming an insulating film on an inner surface of said second groove; removing said side wall; embedding a semiconductor layer doped with impurity of other conductive type in said first and second grooves; forming a gate insulating film on the surface of said semiconductor substrate; forming word lines in stripes perpendicular to said embedded digit lines on said gate insulating film; and diffusing said impurity of the other conductive type in said semiconductor layer through the side surface of said first groove.
In the semiconductor memory device according to the present invention, since the semiconductor layer for composing the embedded digit lines is not directly bonded to the semiconductor substrate by the presence of the insulating film formed inside of the second groove, if the impurity concentration of the semiconductor layer is raised and the resistance of the embedded digit lines is lowered, the junction capacity between the embedded digit lines and the semiconductor substrate can be kept low. As a result, the reading speed of the memory cell can be enhanced.
REFERENCES:
patent: 5962900 (1999-10-01), Chou et al.
patent: 2-150063 (1990-06-01), None
patent: 3217054 (1991-09-01), None
patent: 430556 (1992-02-01), None
patent: 574929 (1993-03-01), None
patent: 5-259410 (1993-10-01), None
patent: 5343416 (1993-12-01), None
patent: 8340054 (1996-12-01), None
patent: 1041411 (1998-02-01), None
NEC Corporation
Wojciechowicz Edward
Young & Thompson
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