Digital-to-analog converter

Details Digital-to-analog converter Digital-to-analog converter

2000-03-24

2001-08-28

Phan, Trong (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

Reexamination Certificate

active

06281825

ABSTRACT:

FIELD OF THE INVENTION
The present invention is in the field of digital-to-analog converters and is more specifically related to a digital-to-analog converter establishing an output voltage by adjusting current.
BACKGROUND OF THE INVENTION
Many electronic circuits use digital-to-analog converters (DACs) for converting digital signals to corresponding analog signals. For example, cellular base stations, wireless communication systems, direct digital frequency synthesizers, signal reconstruction circuits, test equipment, high resolution imaging systems, and arbitrary waveform generators often require high resolution, high speed DACs.
A DAC (or ADC) is an important component for processing video signals and displaying still and sub pictures in imaging systems such as televisions, video tape recorders, digital cameras, and various multi-media apparatuses. More particularly, digitized video signals are common in interpolating, compressing, expanding, and displaying images in multi-media technology such as with computer systems, as well as in the televisions and digital cameras, and such digitized video signals often need to be converted to analog form after digital processing. Accordingly, enhancing the resolution of digital-to-analog converters in the video and multi-media imaging systems is desirable.
FIG. 1
shows the construction of a DAC system having buffer circuits
10
and
40
, a decoder
20
, a delay circuit
30
, a bias voltage supply circuit
50
, and a DAC core circuit
60
. The buffer circuit
10
, which includes two buffers
11
and
12
, receives digital signals (bits) D
1
through D
10
. The decoder
20
receives the four most significant bits D
7
through D
10
and generates a 15-bit digital signal having between zero and fifteen bits in a logic low state, depending on the value represented by the 4-bit input signal to decoder
30
. The delay circuit
30
delays the 6-bit digital signal from the buffer
12
of the buffer circuit
10
and applies a delayed 6-bit digital signal to buffer
42
of the buffer circuit
40
when decoder
20
applies the 15-bit signal to buffer
41
of buffer circuit
40
. DAC core circuit
60
receives the 15-bit and 6-bit digital signals from the buffer circuit
40
at the same time. The bias voltage supply circuit
50
generates bias voltages VBa and VBb to control the DAC core circuit
60
for generation of an appropriate output voltage Vdac for a display apparatus such as electron gun
70
.
The DAC core circuit
60
, as shown in
FIG. 2
, has twenty-one current drive circuits CURI through CUR
21
, each assigned to a corresponding one of the twenty-one digital signals (15 bits+6 bits). The bias voltages VBa and VBb and the digital signals D
1
′ through D
21
′ (and their complements D
1
B′ through D
21
B′) control currents I
1
through I
21
that the current drive circuits conduct to an output summing node N
1
at which output voltage Vdac is generated. When activated each of current drive circuits CUR
2
to CUR
6
provides about twice the current of the preceding one of circuits CUR
1
to CUR
5
. Current drive circuits CUR
7
to CUR
21
all provide about the same current when respective digital signals D
1
′ to D
21
′ are in the logic low state. Output voltage Vdac results from a total current Isum flowing from the node N
1
to a substrate voltage VSS through a resistor R.
FIG. 3
illustrates a situation where the output voltage Vdac from the DAC core circuit
60
is intended to match the shape of an analog wave. Unfortunately, when the output voltage Vdac is near a maximum voltage Vmax, drain-to-source voltages of PMOS transistors PM
1
and PM
2
in current drive circuits CUR
1
and CUR
2
are less than when output voltage is near a minimum voltage Vmin. Accordingly, currents I
1
and I
2
that respectively flow through current drive circuits CUR
1
and CUR
2
to the node N
1
decrease as shown with curve C of
FIG. 4
because variation in the output voltage Vdac at the node N
1
affects the drain-to-source voltages of PMOS transistors PM
1
and PM
2
. For example, current I
2
from current drive circuit CUR
1
is ideally one quarter (¼) of a current I that flows into the common source node of transistors PM
1
and PM
1
′, and current I
4
from current drive circuit CUR
2
is ideally one half (½) of the current I that flows in the common source node of transistors PM
2
and PM
2
′. Correspondingly, as shown in the curve D, currents I
1
′ (ideally ¾ of current I) and I
2
′ (ideally ½ of current I), which flow to reference voltage VSS through respective PMOS transistors PM
1
′ and PM
2
′, increase as output voltage Vdac increases. The drain-to-source current Ids (of PMOS transistors PM
1
and PM
2
) declines, as shown with curve E of
FIG. 5
(curve F is an ideal form), in the saturation region so that the drain-to-source current is influenced by a &lgr;-effect (i.e., channel length modulation effect) induced from node N
1
. Such a decline of the current, as shown in
FIG. 3
, lowers levels of output voltage Vdac to levels B, which are lower than the desired levels A when output voltage Vdac is near maximum voltage Vmax. This can degrade the resolution of a display apparatus using the analog output voltage from the DAC.
SUMMARY OF THE INVENTION
A digital-to-analog converter in accordance with an embodiment of the invention employs a plurality of current drive circuits connected to an output voltage terminal. At least one of the current drive circuits includes: a current division circuit that splits a current from a first power source (e.g., a supply voltage terminal) among a plurality of current paths in response to at least one bias voltage; a current dissipation circuit connected between one of the current paths and a second power source (e.g., a reference voltage terminal); and a current switching circuit for selectably connecting another of the current paths to the voltage terminal. A voltage establishing device connects to the output voltage terminal. The switching circuit transfers a shared current to the voltage terminal in response to corresponding one of the digital bits. The current division circuit can determine the magnitude of the current output to the output voltage terminal, while the current switching circuit determines whether the current drive circuit outputs the current to the voltage output terminal. The current switching circuit also shields the current division circuit from the effects of high output voltage so that the current remains constant and accurate even when the output voltage approaches its maximum.


REFERENCES:
patent: 4405916 (1983-09-01), Hornak et al.
patent: 4583076 (1986-04-01), Luschnig
patent: 5760725 (1998-06-01), Yoshida et al.
patent: 6072415 (2000-06-01), Cheng

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