Selective latch for a domino logic gate

Details Selective latch for a domino logic gate Selective latch for a domino logic gate

1999-12-17

2001-08-28

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S098000

Reexamination Certificate

active

06281710

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to complementary metal oxide semiconductor (CMOS) integrated circuitry and more particularly to such circuitry including a domino logic gate that is selectively latched and which can be evaluated late in an evaluation phase of a clock cycle.
BACKGROUND ART
FIG. 1
is a circuit diagram of a prior art integrated circuit (IC) including a CMOS domino logic gate in combination with circuitry for selectively latching the gate. The circuit of
FIG. 1
includes complementary field effect transistors (FET) carried by integrated circuit chip
10
responsive to a clock source
12
having a high frequency such as 500 MHz. Source
12
derives a substantially rectangular clock wave (CLK)
14
(
FIG. 2
) having a high, positive voltage (i.e., binary one) precharge phase
16
and a low, ground voltage (i.e., binary zero) evaluate phase
18
during each cycle of the clock wave, such that portion
16
has a longer duration than portion
18
.
The clock wave from source
12
and an enable signal
20
from a source (not shown) on chip
10
are combined in AND gate
22
having an inverter input responsive to CLK. Gate
22
, when enabled by a positive voltage from the enable source, responds to CLK to derive CK wave
24
having a positive voltage duration equal to the ground voltage or binary zero portion
18
of wave
14
, FIG.
2
. The positive going transition of CK wave
24
occurs somewhat after the negative going transition of wave of
14
, at a time determined by the inherent delay time of gate
22
.
The CK output signal of gate
22
is applied in parallel to inverter
26
and a first input terminal of NAND gate
28
, both included in selective latching circuit
30
. The output signal of inverter
26
is supplied to a second input terminal of gate
28
by delay circuit
32
. Circuits
26
,
28
and
32
are such that a RCK reset clock output wave
33
of gate
28
has a negative going transition substantially simultaneously with the positive going transition of CK. RCK has a positive going transition that occurs a short time after the negative going transition thereof, at a time determined by the delay time of circuit
32
. The positive going transition of RCK occurs considerably before the negative going transition of CK which follows the positive going transition of CK which caused the negative going transition of RCK.
The output signal of delay circuit
32
is applied to inverter
34
which derives an ECK enable clock wave
35
, having a positive going transition that occurs substantially simultaneously with the positive going transition of RCK wave
33
. ECK wave
35
has a negative going transition that is delayed from its positive going transition by a duration equal to the time between the negative and positive going transitions of CLK wave
14
. Inverter
34
supplies ECK wave
35
to the gate electrode of N-channel field effect transistor
36
, having a grounded source. Transistor
36
and P-channel field effect transistor
38
have source drain paths thereof connected in series between V
DD
positive power supply terminal or rail
40
and ground terminal or rail
42
. Logic circuit
44
, responsive to plural binary logic signals in(s), (indicated by wave
45
) has a pair of output terminals connected between the drain of transistor
36
and the drain of transistor
38
. A parasitic capacitance
46
, shown connected to terminal
48
at the drain of transistor
38
, shunts logic circuit
44
and the drain source path of transistor
36
. Transistors
36
and
38
, logic circuit
44
and parasitic capacitance
46
form part of domino logic gate
50
, which also includes inverter
52
. Inverter
52
has an input terminal connected to be responsive to the voltage level at terminal
48
to derive output signal OH.
The RCK output wave
33
of gate
28
drives the gate of P-channel field effect transistor
55
, having its source drain path connected between +V
DD
terminal
40
and terminal
48
, at the input of inverter
52
. Transistor
55
, when switched on by a low, binary zero value of RCK wave
33
, supplies current to parasitic capacitance
46
and the input terminal of inverter
52
. A low, binary zero value of RCK output wave
33
of gate
28
turns on transistor
38
to precharge capacitance
46
substantially to the +V
DD
voltage at power supply terminal
40
. Simultaneously, transistor
55
supplies a positive voltage to the input of inverter
52
so the inverter derives a low, binary zero output signal. Subsequently, the high value of ECK wave
35
forward biases the drain source path of transistor
36
. If the logic function of logic gate
44
is satisfied by the input signals of the logic gate, there is a low impedance between the logic gate output terminals, resulting in a low impedance discharge path for capacitance
46
through the drain source path of transistor
36
, to reduce the voltage at terminal
48
substantially to ground. Inverter
52
responds to the low voltage at terminal
48
to derive a positive, binary one level to indicate the logic function of gate
44
has been satisfied. The logic function of gate
44
must be satisfied while ECK wave
35
has a high value, i.e., sometime during the evaluate interval
18
of CLK wave
14
or early in the precharge interval
16
immediately following evaluate interval
18
.
P-channel transistors
54
and N-channel transistor
56
, having the source drain paths thereof connected in series between the positive power supply terminal
40
and ground, latch the output signal of inverter
52
. The OH output signal of inverter
52
drives the gates of transistors
54
and
56
in parallel. Hence, for example, if the input signal of inverter
52
is a low voltage, causing the inverter output signal to be a high voltage, the inverter high voltage output forward biases transistor
56
to latch the inverter input to ground and its output to +
VDD
. In contrast, if the input signal of inverter
52
is a high voltage, the inverter output signal is a low voltage that forward biases transistor
54
to latch the inverter input to a high voltage and its output to a low voltage.
If an enable signal is not derived during a particular CLK cycle, the input and output of inverter
52
remain latched at the value they had during the previous CLK cycle when an enable signal was derived. In such a situation, gate
22
derives a low binary zero value throughout the CLK cycle. Consequently, RCK and ECK respectively remain at the high and low voltage levels through the CLK cycle. As a result, capacitance
46
maintains its charge throughout the CLK cycle and no low impedance path can be established through transistor
36
to enable the logic function of gate
44
to be evaluated. Similarly, transistors
55
and
38
remain off and cannot supply charge to capacitance
46
.
As previously discussed, the enable signal must be derived relatively early (before CLK falls) during a CLK cycle in order for the circuit of
FIG. 1
to function properly. However, there are certain instances when it is not possible to provide the enable signal relatively early during the CLK cycle. As integrated circuit chips increase in size and the clock frequencies driving the integrated circuits increase, enable signals from different regions of an integrated circuit chip remote from a domino logic gate and a latch circuit associated with the domino logic gate have a tendency to arrive at the domino logic gate late in a CLK cycle (i.e., during the CLK low phase). The circuit of
FIG. 1
is unable to handle such a situation which can occur, e.g., for chips having 2 cm edges and 500 MHz clock frequencies.
It is, accordingly, an object of the present invention to provide a new and improved circuit for selectively latching a domino logic gate of an integrated circuit chip.
Another object of the invention is to provide a new and improved circuit for selectively latching a domino logic gate on a relatively large integrated circuit chip responsive to a relatively high clock frequency, wherein an enable signal f

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