Output buffer circuit

Details Output buffer circuit Output buffer circuit

1999-10-15

2001-08-21

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S057000, C327S387000

Reexamination Certificate

active

06278294

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an output buffer circuit equipped with a function of converting the signal level between different power-supply voltages and, more particularly, to an output buffer circuit provided with a set of MOS transistors in its last stage.
BACKGROUND ART
FIG. 1
is a circuit diagram of a conventional output buffer circuit disclosed, for example, in Japanese Patent Application No. Hei. 7-176084, depicting the configuration of an input/output circuit of a semiconductor integrated circuit device equipped with a signal level converting function. In an output buffer of an interface circuit which is used between semiconductor integrated circuit devices that operate on different power supply voltages, such a half-latch type signal level converter as shown is used to convert the internal signal level from a low to a high voltage, and the output stage is formed by a push-pull circuit which has a buffer last stage made up of CMOS-structured inverter gates and NMOS-NMOS transistors.
Incidentally, what is intended to mean by the semiconductor integrated circuit device which possesses the signal converting function is a semiconductor integrated circuit device equipped with a function by which the signal voltage provided from a device operating on the power supply voltage in a large scale integrated circuit (LSI) is level converted for output to an external circuit which operates on a power-supply voltage different from that of the internal circuit, and a function by which a signal provided from a device operating on an external power-supply voltage different from the internal one is level converted to the signal voltage of the internal circuit for input thereinto.
In
FIG. 1
, reference numeral
1
denotes an input/output terminal;
2
denotes a control terminal;
3
denotes an input terminal;
4
a
and
4
b
denote first power-supply potential points to which a first power-supply voltage VDD
1
is fed and second power-supply potential points to which a second power-supply voltage VDD
2
is fed, respectively;
5
denotes ground potential points to which the ground potential GND is fed;
6
denotes an input/output control circuit;
7
a
and
7
b
denote a first converter circuit block and a second converter circuit block, respectively; and
8
a
denotes a buffer circuit. These circuit elements constitute an output buffer circuit
91
a
. Reference numeral
10
denotes an input buffer and
11
a static-shielding circuit.
To the input/output terminal
1
is connected an internal circuit via the input buffer
10
. Connected further to the input/output terminal
1
via the output buffer circuit
91
a
are the control terminal
2
which is supplied with a control signal IN
1
from the internal circuit and the input terminal
3
which is supplied with an output signal IN
2
from the internal circuit.
The output buffer circuit
91
a
is composed principally of the input/output control circuit
6
, the signal level converter circuit
7
and the buffer circuit
8
a
, and the control terminal
2
and the input terminal
3
are connected to the input/output control circuit
6
. The input/output control circuit
6
outputs to the signal level converter circuit
7
, and the signal level converter circuit
7
outputs to the buffer circuit
8
a
via connection points N
13
and N
23
.
The input/output control circuit
6
and the first converter circuit block
7
a
forming the first half part of the signal level converter circuit
8
operate on the first power-supply voltage VDD
1
, which is also the power-supply voltage of the internal circuit, and the ground potential GND. On the other hand, the second converter circuit forming the second half part of the signal level converter circuit
7
and the buffer circuit
8
a
operate on the second power-supply voltage VDD
2
, which is generally higher in voltage level than the first power-supply voltage VDD
1
, and the ground potential. The first power-supply voltage VDD
2
and the second power-supply voltage VDD
2
are supplied via the power-supply potential points
4
a
and
4
b
, respectively, and the ground potential GND is supplied via the ground potential points
5
.
A description will be given below of the cases where the control signal IN
1
and the output signal IN
2
that are applied to the control terminal
2
and the input terminal
3
, respectively, are at the “H” level and at the “L” level.
When the control signal IN
1
is at the “H” level, the output signal IN
2
is at the “L” level and the signal level converter circuit
7
forces the connection points N
13
and N
23
to the “L” level (the ground potential GND) and the “H” level (the second power-supply voltage VDD
2
), respectively. As a result, transistors Q
13
and Q
14
of the buffer circuit
8
a
both turn OFF, making the buffer circuit
8
a
high-impedance relative to the input/output terminal
1
. Hence, an external signal fed to the input/output terminal
1
is transmitted to the input buffer
10
with no loss.
On the other hand, when the control signal IN
1
is at the “L” level and the output signal IN
2
at the “L” level, the signal level converter circuit
7
forces either of the connection points N
13
and N
23
to the “L” level. As a result, the transistors Q
13
and Q
14
of the buffer circuit
8
a
turn ON and OFF, respectively, making the input/output terminal
1
“L” level.
And, when the control signal IN
1
is the “L” level and the output signal IN
2
at the “H” level, the signal level converter circuit
7
forces either of the connection points N
13
and N
14
to the “H” level. As a result, the transistors Q
13
and Q
14
of the buffer circuit
8
a
turn ON and OFF, respectively, making the input/output terminal
1
“H” level.
FIG. 2
schematically illustrates in section the transistors Q
13
and Q
14
forming the last stage of the buffer circuit
8
a
. Reference numeral
1
denotes an input/output terminal,
4
b
a second power-supply potential point,
5
a ground potential point, and N
15
and N
24
connection points. In P wells on a P-type semiconductor substrate connected to the ground potential point GND there are formed the NMOS transistors Q
13
and Q
14
. The NMOS transistor Q
13
has its drain electrode connected to the second power-supply potential point
4
b
, its gate electrode connected to the connection point N
15
, its source electrode connected to the input/output terminal
1
and its P well potential connected to the ground potential point
5
. The NMOS transistor Q
14
has its source electrode connected to ground potential point
5
, its gate electrode connected to the connection point N
24
, its drain electrode connected to the output terminal
1
and its P well potential connected to the ground potential point
5
.
FIG. 3
is a circuit diagram of another example of the conventional output buffer circuit, depicting the configuration of an input/output circuit of a semiconductor integrated circuit device equipped with the signal level conversion facility. Reference numeral
8
b
denotes a buffer circuit, which is a substitute for the buffer circuit
8
a
of the configuration shown in FIG.
1
. More specifically, the buffer circuit
8
b
has a CMOS push-pull type output stage by replacing a PMOS transistor Q
15
for the NMOS transistor Q
13
in the final stage of the buffer circuit
8
a
and omits an inverter gate G
18
. Reference numeral
91
b
denotes the output buffer circuit.
FIG. 4
depicts in section the transistors Q
15
and Q
14
forming the final stage of the buffer circuit
8
b
. Reference numeral
1
denotes an input/output terminal,
4
b
a second power-supply potential point,
5
a ground potential point, N
14
and N
24
connection points, and Q
14
and Q
15
an NMOS and a PMOS transistor. In a P well on a P-type semiconductor substrate connected to the ground potential point GND there is formed the NMOS transistor Q
14
, which has its source electrode connected to the input/output terminal
1
and its P well potential connected to the ground potential point
5
. On the other hand, the PMOS transistor Q
15
is

Affiliated with

Also associated with

Rating

Output buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output buffer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2441468