Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1998-12-16
2001-03-06
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S159000, C438S162000, C438S482000, C438S484000
Reexamination Certificate
active
06197625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a thin film transistor having a vertical offset layer which prevents damages on an active layer due to etching plasma by preserving the vertical offset layer during an etching process when forming a divided ohmic contact layer.
2. Discussion of the Related Art
The development of laser crystallization enables fabrication of polycrystalline silicon thin film transistor (“TFT”) on a large-scale glass substrate at normal temperatures used for fabricating amorphous silicon TFTs. Compared to an amorphous silicon TFT, a polycrystalline silicon TFT has higher mobility electrons and holes and enables the formation of a complementary MOS thin film transistor (“CMOS TFT”).
A liquid crystal display (“LCD”) using polycrystalline silicon TFTs includes a driver and a pixel array on a glass substrate. The TFTs in the driver perform fast switching operations due to the desirable characteristic of polycrystalline silicon. However, the TFTs for switching pixels in the pixel array degrade image quality because the voltage width of pixel electrodes is broadened due to a large drain current during the off-state of the TFT. A lightly doped drain or an offset structure have been applied to TFTs in order to reduce the off current in a pixel array.
FIGS. 1A
to
1
D are cross-sectional views illustrating a process of fabricating a TFT having a vertical offset layer according to a first technique of the related art. Referring to
FIG. 1A
, a gate electrode
10
is formed on an insulating substrate
100
, and a first insulating layer
11
is deposited over the gate electrode and an exposed surface of the substrate
100
. An amorphous silicon layer is deposited on the first insulating layer
11
and crystallized by a laser beam. An active layer
12
is then formed by etching the crystallized silicon layer using photolithography. A conventional back-exposure method may be used in the photolithography process.
Referring to
FIG. 1B
, an amorphous silicon layer and an amorphous silicon layer heavily doped with impurities are successively deposited over the active layer
12
and an exposed surface of the substrate
100
. An ohmic contact layer
14
is formed by patterning the heavily-doped amorphous silicon layer with photolithography, and a vertical offset layer
13
is formed by etching the amorphous silicon layer under the ohmic contact layer
14
.
Referring to
FIG. 1C
, a source electrode
15
S and a drain electrode
15
D are formed by disposing a conductive layer on the ohmic contact layer
14
and an exposed surface of the substrate
100
, and by etching the conductive layer using photolithography.
Referring to
FIG. 1D
, a part of the ohmic contact layer
14
which is not protected by the source and drain electrodes
15
S and
15
D (which act as etch masks) is removed by etching. The exposed portions of the vertical offset layer
13
not covered by the remaining ohmic contact layer
14
is also removed by etching.
In the above technique of the related art, as shown in
FIG. 1D
, the ohmic contact layer
14
is divided into two portions for the purpose of switching the TFT. This is done by the etching process using the source and the drain electrodes
15
S and
15
D as etch masks. Generally, the ohmic contact layer
14
is patterned by a dry etch method which removes the etched layer which has been reacted with a plasma in a vacuum chamber and become volatile.
However, when the ohmic contact layer
14
is divided by etching according to the related art, a surface of the active layer
12
is exposed during the process of dividing the vertical offset layer
13
. The exposed portion of the active layer
12
is generally damaged and partially etched by the plasma during etching, thereby degrading the characteristics of the TFT.
FIGS. 2A
to
2
D are cross-sectional views illustrating a process of fabricating a TFT having a vertical offset layer according to a second technique of the related art. Referring to
FIG. 2A
, a gate electrode
20
is formed on an insulating substrate
200
, and a first insulating layer
21
is deposited over the gate electrode and an exposed surface of the substrate. An amorphous silicon layer is formed on the first insulating layer
21
and subsequently crystallized by laser crystallization. An active layer
22
is formed by patterning the crystallized layer using photolithography. A conventional back-exposure method may be used in the photolithography process.
Referring to
FIG. 2B
, a vertical offset layer
23
is formed on the active layer
22
by depositing another amorphous silicon layer over the active layer
22
and an exposed surface of the substrate
200
, and subsequently etching the amorphous layer using photolithography. Referring to
FIG. 2C
, a heavily-doped amorphous silicon layer
24
a
and a conductive layer
25
a
are successively deposited over the vertical offset layer
23
and an exposed surface of the substrate
200
. Referring to
FIG. 2D
, source and drain electrodes
25
S and
25
D are formed by etching the conductive layer
25
a
using photolithography. The amorphous silicon layer
24
a
is etched by using the source and the drain electrodes
25
S and
25
D as etch masks to form an ohmic contact layer
24
having two portions divided from each other.
In the above techniques of the related art, the step of depositing an amorphous silicon layer to form the vertical offset layer and the step of depositing a heavily-doped amorphous silicon layer to form the ohmic contact layer are processed non-successively. Thus, the substrate is transferred from one processing chamber to another for depositing various materials, which makes defects state at the interface between the amorphous silicon layer and doped amorphous silicon layer.
Moreover, each depositing step requires its own cleaning process. As a result, the manufacturing processes are time-consuming and complicated. The complicated manufacturing processes render a lower yield.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a thin film transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of fabricating a TFT which simplifies the fabrication process and prevents damages on an active layer by depositing successively an amorphous silicon layer for forming a vertical offset layer on the active layer and a heavily-doped amorphous silicon layer for forming an ohmic contact layer and by preserving the vertical offset layer when the ohmic contact layer is etched to form a divided layer.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of forming a gate electrode on an insulating substrate, forming a first insulating layer over the gate electrode and an exposed surface of the insulating substrate, forming an active layer on the first insulating layer, forming successively an amorphous silicon layer and a heavily-doped amorphous silicon layer on the whole substrate surface including the active layer, forming a vertical offset layer and an ohmic contact layer by simultaneously patterning the heavily-doped amorphous silicon layer and the amorphous silicon layer, forming a source electrode and a drain electrode connected to the ohmic contact layer, and removing an exposed portion of the ohmic contact layer by etching the ohmic contact layer using the source electrode and the drain electrode as etch masks.
In ano
Elms Richard
Lebentritt Michael S.
LG. Philips LCD Co. Ltd.
Long Aldridge & Norman LLP
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