Semiconductor memory device allowing reliable repairing of a...

Details Semiconductor memory device allowing reliable repairing of a... Semiconductor memory device allowing reliable repairing of a...

2000-04-10

2001-01-23

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

06178127

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory device, and particularly to a semiconductor memory device including a redundant column for repairing a defective memory cell column by replacement. More particularly, the invention relates to repairing of a defective column in the semiconductor memory device which has a plurality of memory blocks each having a redundant column and performs input/output of multi-bit data.
2. Description of the Background Art
Conventional semiconductor memory devices such as a static random access memory and a dynamic random access memory, which will be referred to as an “SRAM” and a “DRAM” hereinafter, respectively, includes redundant circuits for improving a product yield. If a defect is present in a memory portion (memory cell array) of a produced semiconductor memory device, this defective memory portion is repaired by the function of the redundant circuit. This redundant circuit usually includes a redundant row for repairing a row containing a defective memory cell in the memory cell array as well as a redundant column for repairing a column containing a defective memory cell. The defective row or column is replaced with a redundant row or column so that the defective memory cell is equivalently repaired.
FIG. 18
schematically shows a whole structure of a conventional SRAM. In
FIG. 18
, an SRAM 900 includes a plurality of memory blocks BK
1
-BKn each including a plurality of static memory cells arranged in rows and columns as well as a redundant column, and a block selector
1
for decoding a block address signal Z applied through an address buffer
4
to produce block select signals BS
1
-BSn for selecting one of memory blocks BK
1
-BKn. When the SRAM has a memory capacity of 4 Mbits, 64 memory blocks BK
1
-BK
64
are included, and each memory block BK has a memory capacity of 64 Kbits. Data access (data write/read) is performed on a memory cell block selected by block selector
1
.
SRAM 900 further includes an address buffer
2
to receive an externally applied row address signal RA for producing an internal row address signal X, an address buffer
3
to receive an externally applied column address signal for producing an internal column address signal Y, an address buffer
4
to receive an externally applied block address signal BA for producing an internal block address signal Z, input buffers
5
a
and
5
b
to receive input data DIa and DIb for producing internal write data on internal data line pairs DB
1
and DB
2
, respectively, output buffers
6
a
and
6
b
to buffer internal read data DATA
1
and DATA
2
on internal data line pairs DB
1
and DB
2
for producing external read data DOa and DOb, respectively, and a read/write control circuit
7
responsive to an externally applied chip select signal /CS and an externally applied write enable signal /WE for producing an operation control signal WCON for buffers
5
a,
5
b,
6
a
and
6
b
to control write/read operations for a selected memory block.
SRAM 900 operates statically, and address buffers
2
,
3
and
4
produce internal address signals X, Y and Z from address signals RA, CA and BA supplied thereto, respectively. When chip select signal /CS attains the active state at L-level, SRAM 900 is set to the selected state, and data access is performed. Writing or reading of data is executed depending on whether write enable signal /WE is at H-level or L-level.
Internal data line pairs DB
1
and DB
2
are provided commonly to memory blocks BK
1
-BKn, and access to data of 2 bits is performed on the selected memory block.
Each of memory blocks BK
1
-BKn includes one redundant column. For designating which of internal data line pairs DB
1
and DB
2
is to be connected to a redundant column, replacement IO program circuits RIP
1
-RIPn are provided for memory blocks BK
1
-BKn, respectively. Further, memory blocks BK
1
-BKn are provided with replacement column address program circuits RAP
1
-RAPn each for storing a defective column address designating a defective column to be repaired, respectively.
When block selector
1
generates a block select signal BSi (i=1−n) selecting a memory block BKi, a corresponding redundant column is selected in memory block BKi, and the redundant column is connected to one of internal data line pairs DB
1
and DB
2
in accordance with the information stored in replacement IO program circuit RIPi. Thus, a defective column in each memory block BK can be repaired independently of the other memory blocks.
FIG. 19
schematically shows a structure of memory blocks BK
1
-BKn shown in FIG.
18
. Memory blocks BK
1
-BKn have the same structure, and
FIG. 19
shows memory block BK
1
as a representative.
In
FIG. 19
, memory block BK
1
includes memory sub-blocks
910
a
and
910
b
provided corresponding to internal data line pairs DB
1
and DB
2
, respectively, and a redundant column block
930
provided commonly to memory sub-blocks
910
a
and
910
b.
A row decoder
920
is provided commonly to memory sub-blocks
910
a
and
910
b
as well as redundant column block
930
. Row decoder
920
is activated in response to activation of block select signal BS
1
received from block selector
1
shown in
FIG. 18
, to decode internal row address signal X received from address buffer
2
shown in FIG.
18
and drive addressed rows in memory sub-blocks
910
and
910
b
as well as redundant column block
930
to the selected state.
Memory sub-block
910
a
includes a memory cell array
911
a
having a plurality of static memory cells arranged in rows and columns, bit line load circuits
912
a
arranged corresponding to the respective columns (bit line pairs) in memory cell array
911
a
for supplying a column current to corresponding bit line pairs, a column decoder
913
a
to decode an internal column address signal T received from address buffer
3
shown in
FIG. 18
for producing a column select signal, multiplexers
914
a
provided corresponding to the respective columns in memory cell array
911
a
for connecting a selected column in memory cell array
911
a
to internal IO line pair I/Oa in accordance with the column select signal from column decoder
913
a,
a sense amplifier
916
a
selectively activated in response to write control signal WCON from read/write control circuit
7
and block select signal BS
1
, to amplify the internal read data on internal IO line pair I/Oa for transmission onto internal data line pair DB
1
, and a write buffer
915
a
selectively activated in response to block select signal BS
1
and write control signal WCON, to amplify the data on internal data line pair DB
1
for transmission onto internal IO line pair I/Oa.
Sense amplifier
916
a
and write buffer
915
a
are selectively activated in accordance with write control signal WCON when block select signal BS
1
is active. When block select signal BS
1
is inactive, sense amplifier
916
a
and write buffer
915
are set to an output high impedance state. Column decoder
913
a
executes the column selection in accordance with internal column address signal Y applied thereto.
Memory sub-block
910
b
has a structure similar to that of memory sub-block
910
a,
and includes a memory cell array
911
b,
a bit line load circuit
912
b,
a column decoder
913
b,
a multiplexer
914
b,
a sense amplifier
916
b
and a write buffer
915
b.
Sense amplifier
916
b
and write buffer
915
b
couple internal data line pair DB to internal IO line pair I/Ob when made active.
Redundant column block
930
has a redundant column
931
having the same rows as memory cell arrays
911
a
and
911
b,
a redundant column decoder
933
to generate a redundant column select signal in accordance with output signals of replacement column address program circuit RAP
1
and replacement IO program circuit RIP
1
while inhibiting the column selecting operation of column decoders
913
a
and
913
b,
a multiplexer (MUX)
934
to connect redundant column
931
to one of internal IO line pairs I/Oa and I/Ob in accordance with the select signal o

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