Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-30
2001-08-21
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S649000, C438S672000, C438S675000, C438S682000
Reexamination Certificate
active
06277739
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to form semiconductor devices, and more specifically to a method used to form a barrier layer in a high aspect ratio contact hole, to protect an underlying metal silicide layer from processing conditions used during deposition of an overlying refractory metal layer.
(2) Description of Prior Art
The use of metal silicide layers, located overlying conductive regions in a semiconductor substrate and underlying metal interconnect structures, has allowed decreased metal line resistance, and thus improved semiconductor device performance to be realized via the reduction in performance degrading resistance—capacitance (RC), values. However the use of sub-quarter micron features, used with aggressive semiconductor device designs, have resulted in the creation of high aspect ratios contact holes in insulator layers, which can create problems when attempting to form metal silicide layers, on conductive regions, exposed at the bottom of these high aspect ratio contact holes. The ability to form a metal silicide layer, and an overlying barrier layer needed to protect the metal silicide layer from subsequent process steps such as deposition of a refractory metal layer, becomes more difficult as the aspect ratio of the contact hole increases. This invention will teach a novel method of forming these layers in deep, narrow diameter, contact holes, via directionally implanting the metal component needed for both the metal silicide layer, and overlying barrier layer, directly into a conductive region of the semiconductor substrate, exposed at the bottom of the contact hole. Prior art such as Lee et al, in U.S. Pat. No. 5,552,340, describe a method of forming a barrier layer, overlying a metal silicide layer, located at the bottom of a contact hole, via vapor deposition of the metal layer needed for both silicide and barrier formation. The metal deposition procedure used in this prior art, in addition to difficulties encountered with uniform deposition at the bottom of high aspect ratio contact holes, also results in deposition of metal on the sides of the contact hole which either has to be subsequently remove, or remains to limit the space in the contact hole to be occupied by a low resistance metal plug structure. The present invention however offers the advantage of directionally placing the metal source at the bottom of a high aspect ratio contact hole, without metal being formed on, and than having to be removed, from the sides of the contact hole.
SUMMARY OF THE INVENTION
It is an object of this invention to form a metal silicide layer on a conductive region in a semiconductor substrate, exposed at the bottom of a high aspect ratio contact hole.
It is another object of this invention to selectively form a barrier layer on the metal silicide layer, located at the bottom of the high aspect ratio contact hole.
It is still another object of this invention to form the metal silicide layer, located at the bottom of a high aspect ratio contact hole, via implantation of metal ions into a conductive region exposed in the bottom of the high aspect ratio contact hole, and to selectively form the overlying barrier layer, during an anneal cycle performed in a nitrogen containing ambient.
In accordance with the present invention a method of selectively forming a metal silicide layer, and an overlying barrier layer, on a conducive region in a semiconductor substrate, exposed at the bottom of a high aspect ratio contact hole, is described. A first embodiment of this invention entails formation of a high aspect ratio contact hole, opened in an insulator layer, exposing a conductive region in a semiconductor substrate. Metal ions are next directionally implanted into a top portion of the exposed conductive region, as well as into the top surface of the insulator layer in which the high aspect ratio contact hole was formed in. An anneal procedure, performed in a nitrogen ambient, results in the formation of a metal silicide layer on the conductive region exposed at the bottom of the high aspect ratio contact hole, and also results in the formation of a barrier layer, comprised of the implanted metal and nitrogen, overlying the metal silicide layer. The metals ions located in a top portion of the insulator layer, remain unreacted. Deposition of a conductive metal layer completely filling the high aspect ratio contact hole is followed by removal of the portion of the conductive metal layer located on the top surface of the insulator layer, resulting in a conductive metal plug structure, in the high aspect ratio contact hole, overlying the barrier layer—metal silicide layer, located at the bottom of the high aspect ratio contact hole. Formation of a metal interconnect structure, overlying and contacting the conductive metal plug structure, is preceded by a pre-clean procedure which removes a top portion of the insulator layer, containing the unreacted metal ions.
A second embodiment of this invention entails the deposition of a second barrier layer, along with the deposition of a conductive metal layer, completely filling the high aspect ratio contact hole, and overlying and contacting a first barrier layer—metal silicide layer, located at the bottom of the high aspect ratio contact hole. Removal of the second barrier layer and of the conductive metal layer, from the top surface of the insulator layer, result in the definition of a conductive metal plug structure and a second barrier layer, overlying the selectively formed first barrier layer—metal silicide layer, located at the bottom of a high aspect ratio contact hole. A pre-metal clean, followed by metal deposition results in the metal interconnect structure, overlying and contacting the conductive metal plug structure.
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patent: 5552340 (1996-09-01), Lee et al.
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patent: 5899741 (1999-05-01), Tseng et al.
patent: 6100186 (2000-08-01), Hill
patent: 6177338 (2001-01-01), Liaw et al.
patent: 6180513 (2001-01-01), Otsuka et al.
patent: 6187675 (2001-02-01), Buynoski
Ackerman Stephen B.
Picardat Kevin M.
Saile George O.
Vanguard International Semiconductor Corporation
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